Slide 1: 晶心科技 投資者說明會
晶心科技 投資者說明會 張弘毅 發言人 113年11月19日
Slide 2: 投資安全聲明
投資安全聲明 除本文包含的歷史資訊外，本演示文稿中涉及的事項均為前 瞻性陳述，涉及某些可能導致實際結果出現重大差異的風險 和不確定性，包括但不限於天氣、競爭產品和定價的影響、 半導體產品供需的全行業變化、快速的技術變革、半導體行 業週期、 和一般經濟狀況。 除法律要求外，晶心不承擔因新資訊、未來事件或其他原因 而更新任何前瞻性陳述的義務。 2
Slide 3: 報告標題
報告標題 晶心公司簡介 財務與經營狀況 關鍵應用與趨勢 研發暨技術能量 3
Slide 4: 晶心科技公司簡介
晶心科技公司簡介 晶心亮點 •2005年3月設立於台灣新竹科學園區。 •根基穩健的高科技上市公司。 •員工人數超過500人；80%為工程師。 •獲得TSMC 2015年新的 IP OIP Award 。 •晉升為RISC-V國際聯盟(前身為RISC-V基金會) 首席會員。 (2020) •獲得Al Global Media頒發「2020年最傑出嵌入式處理器IP供應商」。 •EE Awards亞洲金選獎 -「Taiwan 產品獎」,「Asia 企業獎」(2021) •2023亞太區 前五百大高成長企業 晶心任務 • 創新架構高效能/低功耗嵌入式處理器。 晶心利基 • 智能及環保之電子設備 • 雲
Slide 5: 晶心科技公司現況
晶心科技公司現況 晶心科技指標性資訊 19 Years 500+ 400+ Customers 14Bn+ SoC Pureplay CPU vendor Employee , > 80% R&D Licensing AndesCore™ Total Customer Shipment 2023年營運數字 Revenue $ Growth License $ Growth Royalty $ Growth SoC Shipping Q’ty 1.05 Bn, NT$ 18.3% YoY -1.2% YoY 2.1Bn 13.5% YoY 晶心科技參與RISC-V International (
Slide 6: 財務與經營狀況
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Slide 7: 2024/Q1~Q3 整體營收分析
2024/Q1 ~ Q3 整體營收分析 YoY QoQ YoY +73.1 % +53.9 % +41.2 % (NTD ’000) (NTD ’000) Taking RISC-V® Mainstream 7
Slide 8: 2024/Q1~Q3 授權金營收分析
2024/Q1 ~ Q3 授權金營收分析 YoY QoQ YoY +114.8 % +81.2 % +59.6 % (NTD ’000) (NTD ’000) Taking RISC-V® Mainstream 8
Slide 9: 2024/Q1~Q3 權利金營收分析
2024/Q1 ~ Q3 權利金營收分析 YoY QoQ +29.3 % YoY +25.8 % +29.5 % (NTD ’000) (NTD ’000) Taking RISC-V® Mainstream 9
Slide 10: 2024 Q1-Q3 營收商業模式分析
2024 Q1-Q3 營收商業模式分析 Taking RISC-V® Mainstream 10
Slide 11: 2024 Q1-Q3 區域別營收分析
2024 Q1-Q3 區域別營收分析 Taking RISC-V® Mainstream 11
Slide 12: 2024 Q1-Q3 應用類別營收分析
2024 Q1-Q3 應用類別營收分析 Taking RISC-V® Mainstream 12
Slide 13: 2021 to 2024 (Q1-Q3) 應用類別營收分析
2021 to 2024 (Q1-Q3) 應用類別營收分析 (NTD ’000) Taking RISC-V® Mainstream 13
Slide 14: 歷年授權金結構與比較
歷年授權金結構與比較 (NTD ’000) License Revenue Taking RISC-V® Mainstream 14
Slide 15: 歷年權利金結構與比較
歷年權利金結構與比較 (NTD ’000) Royalty Revenue Taking RISC-V® Mainstream 15
Slide 16: 2024 Q3 營業費用分析
2024 Q3 營業費用分析 YoY QoQ +28.6 % -4.9 % (NTD ’000) Taking RISC-V® Mainstream 16
Slide 17: 2024 Q1-Q3 營業費用分析
2024 Q1-Q3 營業費用分析 YoY +36% (NTD ’000) Taking RISC-V® Mainstream 17
Slide 18: 2024 Q3 每股盈餘分析
2024 Q3 每股盈餘分析 YoY QoQ $- 2.09 $ +1.50 (NTD) Taking RISC-V® Mainstream 18
Slide 19: 2024 Q1-Q3 每股盈餘分析
2024 Q1-Q3 每股盈餘分析 YoY $ -2.73 (NTD ) Taking RISC-V® Mainstream 19
Slide 20: 關鍵應用與趨勢
關鍵應用與趨勢 20
Slide 21: The Key Applications & The Trend
The Key Applications & The Trend The global Internet of The market size in the Things (IoT) market size is Artificial Intelligence projected to grow from market is projected to $714.48 billion in 2024 to reach US$305.90bn in $4,062.34 billion by 2032, 2024. at a CAGR of 24.3%... The market size is R
Slide 22: Fast Growing Automotive MCU Markets
• Fast Growing Automotive MCU Markets Semiconductor devices in vehicle are growing fast! Global automobile MCU market size in 2024 will reach USD$10.48B, and $16B at 2029, CAGR 8.92% https://www.mordorintelligence.com/industry-reports/global- automotive-mcu-market The total number of MCUs will
Slide 23: CMOS Image Sensor Chip (ASIL-B)
CMOS Image Sensor Chip (ASIL-B) MetaSilicon MAT series CMOS image sensor chips use the AndesCore N25F-SE processor to achieve a high level of safety and reliability. SOC includes LOFIC (Lateral Overflow Integration Capacitor) + DCG (Dual Conversion Gain) HDR (High-Dynamic Range), dual-row ADC, M
Slide 24: Touch and Display Driver Integration (TDDI) SoC
Touch and Display Driver Integration (TDDI) SoC ILITEK’s ILI6600A supports up to 3 chips cascading and provides the number of colors up to 16.7M. Its IIE (Impressive Image Enhancement) function can achieve high-quality display and visual experience. The ILI6600A uses the ISO 26262 functional saf
Slide 25: Safety Mechanisms Andes FuSA cores Implemented
Safety Mechanisms Andes FuSA cores Implemented Mission Critical Low Power & Security Common Safety Features • Advanced ECC • Address Decoder D45-SE D23-SE N25F-SE 8-stage 3-stage 5-stage • White Noise Protection Single-issue Dual-issue Single-issue • Error Status Indication • Core Trap Status Bus In
Slide 26: RISC-V for Datacenter & Cloud
RISC-V for Datacenter & Cloud RISC-V offers unique Custom computing for AI Achieve your performance Opportunity for and and accelerators other emerging workloads power targets RISC-V CPU core market will grow 115% CAGR, capturing > 14% of all CPU cores by 2025 26
Slide 27: Andes RISC-V Processors to Fit Your AI
Andes RISC-V Processors to Fit Your AI Data center >100 TOPS Automotive Mobile AR/VR >10 TOPS Surveillance • ADAS, HDR • > 10 cameras >1 TOPS Smart Home • Face unlock • Bokeh Andes V-Series Avatar >1 GOPS Smart Camera • (RV64GCPV) • Gesture recognition • Intelligent HMI • SLAM AnDLA™ I-Series • Barg
Slide 28: MTIA: Meta Training/Inference Accelerator
MTIA: Meta Training/Inference Accelerator ISCA 2023 paper, “MTIA: First Generation Silicon Targeting Meta’s Recommendation Systems” Proc-A/B: AX25-V100, an early version of the popular NX27V Custom extensions: for new interfaces, instructions and registers Performs quite well on low and medi
Slide 29: Edge AI With Analog In-Memory Computing
Edge AI With Analog In-Memory Computing TetraMem Analog In-Memory-Computing MX200 (RRAM-based) 8-bit 256x256 (64K) MAC Engines, >30 TOPS/W performance ML core operators (conv, gemm) processed in NPU Remaining operations processed in RISC-V Vector processors and control CPU AXI Bus "Thousands
Slide 30: Edge AI With In-Memory Computing
Edge AI With In-Memory Computing Axelera Metis SoC Targeting Computer Vision applications 4 powerful PE’s, each with digital In-Memory Computing (D-IMC) RISC-V processors for both PE control as well as system control under Linux Powerful 4MB L1 4MB L1 Competitive 214 TOPS/chip , best in class
Slide 31: Endpoint AI
Endpoint AI Renesas R9A06G150 Voice-Control ASSP With 100MHz DSP-capable D25F processor ML-based voice recognition gets >50% speedup by using P-extension Spacetouch SPV60 Intelligent audio processor High performance for customer development 100 GOPS NPU for noise reduction, echo cancellati
Slide 32: AndesAIRE: Andes AI Runs Everywhere
AndesAIRE™: Andes AI Runs Everywhere HW/SW Solutions for AI from the Edge to the Cloud NN models AndesAIRE™ NN SDK AndeSight™ IDE AndesAIRE™ NNPilot™ • GCC/LLVM Toolchains Pruning, Quantization, Optimization, Evaluation • Build, debug, profile Generated C code template Generated NN models • Analys
Slide 33: 研發暨技術能量
Git 35 SSF (0 Ae = Anes 33
Slide 34: Andes RISC-V CPU Cores
Andes RISC-V CPU Cores AX60 Series AX63 AX65 AX66/AX67 AX6X-SE A72~A78; 13-stage OOO Linux MP N1/V1/X1 Categories Power-efficient Mid-range Extended FUSA 45 Series AX45MPV, AX46MPV A53/55, R52/ N45, NX45 D45 D45-SE 8-stage Superscalar A45(MP), AX45(MP) R82, M7 27 Series NX27V A27(L2), AX27(L2) A5/7/
Slide 35: RISC-V Continues to Rapidly Grow
RISC-V Continues to Rapidly RISE: RISC-V Software Ecosystem, a project under LF Europe To accelerate the development of RISC-V open source SW Led by industry leaders Areas to focus over time: Compilers & Toolchains Language Runtimes System Libraries Debug & Profiling Tools Simulato
Slide 36: Andes Partners and RISC-V Ecosystem
Andes Partners and RISC-V Ecosystem Category Partners IP SW and Dev Env. Design Service, Foundries, EDA and others 36
Slide 37: 感謝聆聽
感謝聆聽