Global Unichip : GUC Announces Successful Launch of Industry's First 32G UCIe Silicon on TSMC 3nm and CoWoS Technology

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GUC Announces Successful Launch of Industry's First 32G UCIe Silicon on TSMC 3nm and CoWoS Technology Mar. 13, 2025 News Content: Hsinchu, Taiwan - Mar. 13th, 2025 - Global Unichip Corp. (GUC), the Advanced ASIC Leader, today announced the successful launch of industry's first Universal Chiplet Interconnect Express™ (UCIe™) PHY silicon, achieving a data rate of 32 Gbps per lane, the highest speed defined in the UCIe specification. The 32G UCIe IP, supporting UCIe 2.0, delivers an impressive bandwidth density of 10 Tbps per 1 mm of die edge (5 Tbps/mm full-duplex). This milestone was achieved using TSMC's advanced N3P process and CoWoS® packaging technologies, targeting AI, high-performance computing (HPC), xPU, and networking applications. In this test chip, several dies with North-South and East-West IP orientations are interconnected through CoWoS interposer. The silicon measurements show robust 32Gbps operation with wide horizontal and vertical eye openings. GUC is working aggressively on the full-corner qualification, and the complete silicon report is expected to be available in the coming quarter.To ensure seamless system integration, GUC has developed bridges for AXI, CXS, and CHI buses utilizing the UCIe Streaming Protocol. These bridges are optimized for high traffic density, low power consumption, minimal data transfer latency, and efficient end-to-end flow control - enabling an effortless transition from traditional single-chip Networks-on-Chip (NoC) to chiplet-based architectures. Additionally, the bridges support Dynamic Voltage and Frequency Scaling (DVFS), allowing real-time voltage and frequency adjustments independently of each die without interrupting data flow.GUC's UCIe IP also features advanced reliability capabilities, including UCIe Preventive Monitoring functionality and integrated I/O signal quality monitors from proteanTecs. This technology enables continuous, mission-mode monitoring of signal integrity during data transmission without the need for re-training or disrupting operations. Each signal lane is individually monitored, with real-time detection of power and signal integrity anomalies. Potential defects in bumps and traces are identified early, triggering repair algorithms that replace marginal I/Os with redundant ones to prevent system failures. This proactive approach significantly extends chip lifespan and enhances sys...

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