Nxp Semiconductors N.v. · NASDAQ:NXPI
Nxp Semiconductors — Technical Presentation (May 2018)
72 slides from Nxp Semiconductors's technical presentation, May 31, 2018
Slide 1: LPC80x MCUs Are Your 32-Bit Answer
THINKING ABOUT MIGRATING FROM 8-BIT? WAIT NO LONGER – LPC80X MCUS ARE YOUR 32-BIT ANSWER! CARLOS MENDOZA – SYSTEMS & APPLICATIONS ENGINEER OMAR CRUZ – PRODUCT MARKETER MAY 31, 2018 NXP and the NXP logo are trademarks of NXP B.V. All other product or service names are the property of their respective
Slide 2: Agenda
Agenda • Introduction • LPC80x MCU Family Overview • User case/application • Arm® Cortex®-M0+ • Low Power Modes • Memory (Flash + ROM) • Clock Generation • GPIO • Dual Power Supply • Analog • Other Peripherals • Enablement • Summary PUBLIC 1
Slide 3: LPC Microcontrollers
LPC MICROCONTROLLERS Broad Market Leader Architecting Scalable MCU Families with Flexible Integration Enabling Fast Time To Market & Platform Re-use Innovative 1 2 3 4 5 Ecosystem & Supply, Longevity, Local Extensive Arm®-based Partners & Quality Support Network Software & Tools MCU Portfolio » Acce
Slide 4: General Purpose MCU Roadmap | Power Efficient & Embedded Flash
General Purpose MCU Roadmap | Power Efficient & Embedded Flash Arm LPC546xx LPC540xx LPC54S0xx CM4 150MHz+ 180MHz Cortex-M4 180MHz Cortex-M4 LPC540xx with 512KB F, 200KB S 0KB F, 360KB S With Security Enhancements Advanced Xtal-less FS USB, HS USB, Xtal-less FS USB, HS USB, TFT-LCD, 10/100 ENET, TFT
Slide 5: LPC80x MCU Family Overview
LPC80X MCU FAMILY OVERVIEW PUBLIC 4
Slide 6: LPC802 MCUs: 15MHz Cortex-M0+ with 16KB Flash
LPC802 MCUs: 15MHz Cortex-M0+ with 16KB Flash LPC802 EEPROM based Flash 16 kB Performance ARM • 15-MHz Cortex-M0+ ARM core AHB-LITE Bus CORTEX-M0+ SRAM 15 MHz 2 kB • 16 kB EEPROM-based Flash, with 64 B page size IOP ROM • 2 kB RAM GPIO CRP Up to 17 Serial connectivity and GPIOs Power Control • 1 I2C
Slide 7: LPC804 MCUs: 15MHz Cortex-M0+ with 32KB Flash
LPC804 MCUs: 15MHz Cortex-M0+ with 32KB Flash System • 15-MHz Cortex-M0+ ARM core LPC804 EEPROM based Flash • Up to 32 kB EEPROM-based Flash, with 64 B page size 32 kB ARM • Up to 4 kB RAM AHB-LITE Bus CORTEX-M0+ SRAM 15 MHz 4 kB Serial connectivity and GPIOs IOP ROM • 2 I2C (Fm), 1 SPI, 2 UART GPIO
Slide 8: Excellent Companion Processor
Excellent Companion Processor EEPROM (100K+ R/W cycles) + IO expander (I2C/SPI/UART I/F) EEPROM data storage + Level shifter (e.g. 3.3V->1.8V) + Small logic units (AND/OR/NAND/Flip-Flop, etc.) IO Expander + Power efficient sensor node controller Level shifter + PMU (Power Management Unit) + Cap. tou
Slide 9: Low-Cost Companion MCU for Robotic Vacuum
Low-Cost Companion MCU for Robotic Vacuum Example Application for LPC802 VDD 3V LPC802 LPC802 for broad range of main MCU/MPU Cortex-M0+ resource extension core 16K EEPROM VDD 1.8V • Analog sensor interface (light, motion, CO, etc.) 3V • Digital sensor interface (temp, humidity, smoke, etc.) ADC Mai
Slide 10: LPC800 Series MCU Target Applications
LPC800 Series MCU Target Applications • Power- and size-sensitive control and connectivity tasks such as: − Sensor gateways – connect to & concentrate data from analog and/or digital sensors − End-node connectivity, e.g. NFC, BLE, Zigbee ,etc. − Capacitive touch for HMI − Simple motor control − 8/16
Slide 11: Arm Cortex-M0+ Core Technology Overview
ARM CORTEX-M0+ CORE TECHNOLOGY OVERVIEW PUBLIC 10
Slide 12: Arm Cortex-M0+ Core Technology Overview
Arm Cortex-M0+ Core Technology Overview • High performance 32-bit CPU • 2 stage pipeline • Performance efficiency − 1.77 CoreMark/MHz - 0.93 DMIPS/MHz • Deterministic operation • Single cycle IO • Built-in Nested Vectored Interrupt Controller (NVIC) with Wake-up Interrupt Controller (WIC) • Debug us
Slide 13: Superior Code Density
Superior Code Density 64 Instruction Size for Number of bits 48 Various Processors 32 16 8051 PIC18 PIC24 MSP430/ Cortex-M0+ MSP430X • Leading to superior code density: − In Cortex-M0/M0+ all instructions (except BL) are 16 bits wide instructions − Over 64kB of address space, 8- and 16- processors h
Slide 14: Cortex-M0+ - Energy Efficiency
Cortex-M0+ - Energy Efficiency 2.00 1.80 1.77 CoreMark/MHz Cortex-M0+ runs at a 1.60 much slower clock 1.40 frequency for the same 1.20 required performance 1.00 0.93 ✓>2x CoreMark/mA 0.80 0.74 performance than the 0.67 closest 8/16-bit 0.60 0.54 competitor 0.40 0.20 0.11 0.04 Cortex-M0+ can sle
Slide 15: Cortex-M0+ Micro-Trace Buffer (MTB)
Cortex-M0+ Micro-Trace Buffer (MTB) • Trace store in RAM (non-instructive) • Read over Serial Wire / JTAG (CPU stopped) PUBLIC 14
Slide 16: Cortex-M0+ Vector Table Relocation
Cortex-M0+ Vector Table Relocation • Relocate vector table in other locations in flash or SRAM • Exception vector reconfiguration at runtime PUBLIC 15
Slide 17: Low Power Modes
LOW POWER MODES PUBLIC 16
Slide 18: Low Power Modes
Low Power Modes Low Power Impact Wake-Up Sources Current Current Mode Consumption Consumption (LPC802) (LPC804) System Clock to Cortex-M0+ is stopped. Any peripherals interrupts (SCT, MRT, USART, Peripherals and memories are active. SPI, I2C, CMP) Processor state and registers, peripheral Pin interr
Slide 19: Memory
MEMORY PUBLIC 18
Slide 20: LPC802 MCU Memory Block
LPC802 MCU Memory Block Feature LPC802 as I2C Traditional I2C EEPROM • Flash EEPROM − EEPROM based, no ERASE Capacity (bit) > 64Kbit Typ: 64Kbit needed Page Size 64B - (Byte mode); 64B (Page mode − 1kB virtual sectors with 64-byte Endurance (E/P Typ.: 500K , min: 200K Typ: 1000K (Byte mode) page pro
Slide 21: Code Read Protection Levels
Code Read Protection Levels • Four levels of the Code Read Protection • This feature allows user to Read Code Full Chip Erase Erase Sectors Program Sectors SWD Access enable different levels of security NO CRP Enabled Enabled Enabled Enabled Enabled in the system so that access to the on-chip flash
Slide 22: ROM
ROM PUBLIC 21
Slide 23: Boot ROM
BOOT ROM • 8 KB on-chip ROM BOOT ROM • Bootloader 0x0F001FFF − In-System Programming (ISP) API calls − Update FLASH via USART, I2C or SPI • ROM API − In-Application Programming (IAP) of flash 0x0F000200 memory 0x0F0001FF − Integer divide routines 0x0F000000 Vector table − FRO API • Memory map − 0x0F
Slide 24: Clock Generation Unit
CLOCK GENERATION UNIT PUBLIC 23
Slide 25: Free Running Oscillator (FRO)
Free Running Oscillator (FRO) VDD • Low power internal Free-Running Oscillator − ~74 uA, replaces former “IRC” • Fast startup Iosc − ~50 us • Provides selectable outputs − 15 MHz, 12 MHz or 9 MHz which can be divided • Factory Trimmed 15 MHz/12 MHz/9 MHz CCO − +/- 1% accuracy over 0 C to 70 C CCO •
Slide 26: GPIO
GPIO PUBLIC 25
Slide 27: Flexible I/O Port
Flexible I/O Port • Single cycle access to all port pins • Support high frequency I/O toggling − As fast as CPU_Clock/2 • Enhanced GPIO Pin Manipulation − Capable of simultaneously reading Bit/Byte/Word or toggling up to all I/Os per two instructions − Return pin state anytime regardless of directio
Slide 28: Switch Matrix
Switch Matrix • Movable functions Switch Matrix − Can be assigned to any external pin that UART P0_1 is not power or ground − UART, SPI, I²C, SCT, comparator output, SPI P0_2 CLKOUT, pattern match output, and Ctimer I2C P0_3 SCT P0_4 • Fixed pin functions − Oscillator pins, comparator input, GPIOs −
Slide 29: Dual Power Supply
DUAL POWER SUPPLY PUBLIC 28
Slide 30: Dual Power Supply
Dual Power Supply • Support level shifting without external LPC802 dual supply components and circuit − Save BOM VDDio − 2 different power domains: VDDio, VDD on separate package sides … … ▪ Each package side refers to its side power supply VDD ▪ Digital: 1.71 to 3.6V … … ▪ ADC: 2.5 to 3.6V ▪ DAC: 2
Slide 31: Analog
ANALOG PUBLIC 30
Slide 32: Cap Touch – LPC804 MCUs
Cap Touch – LPC804 MCUs • Similar IP to LPC845 Cap Touch • Mutual capacitive based • Support different shapes of touch − up to 5 keys (pads) − rotary − slider • Capable of gesture recognition • FreeMaster based PC calibration tool • Passed IEC61000-4-6 certification/current injection test PUBLIC 31
Slide 33: Analog Peripherals
Analog Peripherals Analog to Digital Converter Analog Comparator • 2-bit successive approximation • 5 inputs are multiplexed separately to the positive • Input multiplexing among 12 pins voltage input and negative inputs • 12-bit conversion rate up to 480 Ksps • The Internal voltage reference (0.9 V
Slide 34: Programmable Logic Unit (PLU)
PROGRAMMABLE LOGIC UNIT (PLU) PUBLIC 33
Slide 35: PLU Features
PLU Features • Create combinational and sequential LUT_out(25:1) LUT0_in (4:0) LUT_out(0) logic networks LUT0 State (3:0) • 32-bit Truth Table - Look-up Table (LUT) based PLU in (5:0) • 4 state flip-flops − Clocked by external from LUT_out(25:2,0) LUT1_in (4:0) LUT_out(1) LUT1 PLU out (7:0) PLU_CLKI
Slide 36: Other Peripherals
OTHER PERIPHERALS PUBLIC 35
Slide 37: Other Peripherals
Other Peripherals Timers Serial Interfaces • Standard 32-bit Timer • USART • Multi-Rate timer (MRT) • I²C • SPI • Self wake-up timer (WKT) • Windowed watchdog timer (24-bit timer) • SysTick Timer (24-bit timer) Cyclic Redundancy Check (CRC) Engine • Supports three common polynomials CRC- Pattern Mat
Slide 38: Enablement
ENABLEMENT PUBLIC 37
Slide 39: Enablement: LPCXpresso802 Board (OM40000)
Enablement: LPCXpresso802 Board (OM40000) • LPC802 Arm Cortex-M0+ running at up to 15MHz • On-board CMSIS-DAP debug interface − Supported by MCUXpresso IDE and popular 3rd party IDEs − Includes VCOM port based on LPC11U35 MCU • Debug connector to allow debug to target LPC802 MCU using an external pr
Slide 40: Enablement: LPCXpresso804 Board (OM40001)
Enablement: LPCXpresso804 Board (OM40001) • 3-board set, comprising • 3 User LEDs LPCXpresso804 board with • Reset button PLU and capacitive touch shields • 1Mb Winbond SPI flash • Compatible with MCUXpresso • NXP LM75BDP temperature IDE and other popular sensor toolchains (incl. IAR and Keil) • PLU
Slide 41: MCUXpresso Software and Tools
MCUXpresso Software and Tools for LPC & Kinetis MCUs and i.MX RT crossover processors MCUXpresso IDE Edit, compile, debug and optimize in an intuitive and powerful IDE MCUXpresso SDK Runtime software including peripheral drivers, middleware, RTOS, demos and more MCUXpresso Config Tools Online and de
Slide 42: LPC800 MCU Series Code Bundles
Learn more at: www.nxp.com/LPC80x LPC800 MCU Series Code Bundles • The LPC800 Family of MCUs are ideal for customers who want to make the transition from 8 and 16-bit MCUs to the Cortex® M0/M0+. • Code Bundles consist of software examples to teach users how to program the peripherals at a basic leve
Slide 43: Summary
SUMMARY PUBLIC 42
Slide 44: Summary
Summary • Simplicity • High performance at a low price point • 2-10x higher performance than 8/16-bit MCUs • 2-3x power saving compared to 8/16-bit MCUs • 40-50% smaller code size than 8/16-bit MCUs • Single cycle IO access with high drive capability and PME • Highly integrated features to reduce sy
Slide 45: Related Resources
Related Resources • LPC80x Webpage: http://www.nxp.com/lpc80x • LPCXpresso802 Board: http://www.nxp.com/demoboard/OM40000 • LPCXpresso804 Board: http://www.nxp.com/demoboard/OM40001 • LPC Microcontroller Community: https://community.nxp.com/community/lpc • MCUXpresso Software and Tools: https://www.
Slide 46: Software, Professional Support & Services
Software, Professional Support & Services Complimentary Software & Tools • MCUXpresso, Software Development Kit, Pin Config, Power Estimator/Analyzer Professional Services Complimentary Support • Managing Skills Gaps & Engineering Capacity • NXP Boards • Global Staffing Capability • Communities • Ve
Slide 47: NXP and the NXP logo are trademarks of NXP B.V. All other product or
NXP and the NXP logo are trademarks of NXP B.V. All other product or service names are the property of their respective owners. © 2017 NXP B.V.
Slide 48: Back Up
BACK UP PUBLIC 47
Slide 49: ROM
ROM PUBLIC 48
Slide 50: FLASH programming
FLASH programming • In-System Programming (ISP) ISP Mode Default Pin function ISP Entry Pin – PIO0_12 ISP Mode is entered when ISP Entry Pin is USART (single PIO0_4 is UART0 TX pulled LOW during RESET supply part) PIO0_0 is UART0 RX ISP entry can be disabled using CRP USART (Dual PIO0_9 is UART0 TX
Slide 51: GPIO
GPIO PUBLIC 50
Slide 52: High Drive Pins
High Drive Pins Vcc • Provide high current drive capability (20mA) • Able to directly drive LEDs − Eliminate external drive IC − Save BOM cost and board PCB size • High drive pins − 3 pins: PIO0_2, PIO0_3, PIO0_12 (LPC802) − 5 pins: PIO0_2, PIO0_3, PIO0_12, PIO0_18, and PIO0_20 (LPC804) PUBLIC 51
Slide 53: Clock Generation Unit
CLOCK GENERATION UNIT PUBLIC 52
Slide 54: Clock Generation Unit
Clock Generation Unit Clock Characteristics FRO Sources CLK_IN AHB FRO Oscillator • System clock by default main_clk main_clk • Stable. Quick power up and power LPOSC divider CPU down FRO_DIV • 30/24/18MHz (±1% over 0 C to 70 C) CLK_IN • 1 MHz – 15 MHz Low Power • Low power operation Oscillator • Lo
Slide 55: Analog
ANALOG PUBLIC 54
Slide 56: Analog to Digital Converter
Analog to Digital Converter • 12-bit successive approximation • Input multiplexing among 12 pins • 12-bit conversion rate up to 480 Ksps • Two configurable conversion sequences with independent triggers • Optional automatic high/low threshold comparison and “zero crossing” detection • Power down mod
Slide 57: DAC Feature
DAC Feature VREFP VDDA • 10-bit digital to analog BIAS BIT VALUE (CR.16) CR(15:6) converters • Resistor string architecture R Control logic BIAS BIT • Buffered output R • Power-down mode • IF set the max. conversion time is 2.5us and the maximum current will be 350uA • Selectable speed vs. power R •
Slide 58: Analog Comparator
Analog Comparator • Compares voltage levels on external pins and internal voltages • 5 inputs are multiplexed separately to the positive voltage input and negative inputs • The Internal voltage reference (0.9 V bandgap reference) and DACOUT can be used as either the positive or negative input of the
Slide 59: Debug Module
DEBUG MODULE PUBLIC 58
Slide 60: Emulation and Debugging
Emulation and Debugging • Debug and trace functions are integrated into the ARM Cortex-M0+ • Serial wire debug (SWD: 2 pins) • Supports up to four breakpoints and two watchpoints • Micro Trace Buffer (MTB) supported • Standard JTAG pins (5 pins) supports ONLY boundary scan testing PUBLIC 59
Slide 61: PLU
PLU PUBLIC 60
Slide 62: What's the advantage of PLU?
What’s the advantage of PLU? • Simple glue logic to connect MCU with external components and replace these 7400 LPC804 series. … • State machine design using Flip-flop 7400 • Address decoder • Pattern match • Low-power application. Many peripherals are shut off in deep-sleep and power-down mode, PLU
Slide 63: Other Peripherals
OTHER PERIPHERALS PUBLIC 62
Slide 64: Timers
Timers • Standard 32-bit Timer • Multi-Rate timer (MRT) − Timer with four independent channels − Each channel can generate interrupts ▪ Repeat interrupt mode ▪ One-shot interrupt mode • Self wake-up timer (WKT) − A non-zero value in this 32-bit timer initiates a countdown sequence. Wake-up source fr
Slide 65: Pattern Match Engine (PME)
Pattern Match Engine (PME) • Pin Interrupt generator − Up to 8 pins can be selected to generate interrupts to the core IN0 • Pattern match feature IN1 IN2 − The same 8 pins (above) can be selected from all GPIO pins Pattern IN3 to contribute to a Boolean expression IN4 Match OUT ▪ Example: IN5 Engin
Slide 66: USART/I²C/SPI
USART/I²C/SPI • USART ▪ Synchronous operations on all UARTs ▪ Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous mode for USART functions ▪ Fractional rate divider is shared among all USARTs ▪ Built-in baud rate generator • I²C ▪ Standard-mode, Fast-mode • SPI ▪ Maxi
Slide 67: Cyclic Redundancy Check (CRC) Engine
Cyclic Redundancy Check (CRC) Engine • Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32 − CRC-CCITT: X16 + X12 + X5 + 1 − CRC-16: X16 + X15 + X2 + 1 − CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 • Accept any size of data width per write: 8, 1
Slide 68: Enablement
ENABLEMENT PUBLIC 67
Slide 69: MCUXpresso IDE
Learn more at: www.nxp.com/mcuxpresso/ide MCUXpresso IDE Free Eclipse and GCC-based IDE for C/C++ Product Features development on Kinetis and LPC MCUs and • Feature-rich, unlimited code size, i.MX RT crossover processors optimized for ease-of-use, based on industry standard Eclipse framework for NXP
Slide 70: MCUXpresso SDK
Learn more at: www.nxp.com/mcuxpresso/sdk MCUXpresso SDK The software framework and reference for Kinetis & LPC Product Features MCU application development Architecture: Reference Software: ▪ CMSIS-CORE compatible ▪ Peripheral driver usage examples ▪ Single driver for each peripheral ▪ Application
Slide 71: MCUXpresso Config Tools
Learn more at: www.nxp.com/mcuxpresso/config MCUXpresso Config Tools Integrated configuration and MCUXpresso Config Tools is a suite of evaluation and development tools for LPC configuration tools that helps guide users from first evaluation and Kinetis MCUs to production software development. SDK B
Slide 72: NXP and the NXP logo are trademarks of NXP B.V. All other product or
NXP and the NXP logo are trademarks of NXP B.V. All other product or service names are the property of their respective owners. © 2017 NXP B.V.
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