Gsi Technology, Inc. · NASDAQ:GSIT
Gsi Technology — CMSE 2011
14 slides from Gsi Technology's conference presentation, February 2011
Slide 1: On-Chip ECC: Addressing SRAM SER in a COTS World
On-Chip ECC: Addressing SRAM SER in a COTS World CMSE: February 2011 Bob Haig 4131 Spicewood Springs Rd, Ste F-2 Austin, TX 78759 512-346-7180 ext.204 bhaig@gsitechnology.com
Slide 2: Taking Ownership of SER
Taking Ownership of SER • ECC is commonly utilized with SRAMs in data- critical applications. • Increasingly rare for SRAM controllers to be designed “in house”. • Availability of 3rd party controllers is limited, and they often do not support ECC. • On-chip ECC removes the burden from the controlle
Slide 3: Implementation Overview
Implementation Overview • Hamming Code algorithm. • Single-bit error detection and correction. • Implemented across the 18b DDR data word transmitted on each external 9b byte lane. • 5 parity bits per 18 data bits.
Slide 4: Efficiency Benefits
Efficiency Benefits On Chip ECC External ECC 18b ECC 72b ECC 36b ECC 18b ECC x36 part|x18 part) x36 part|x18 part|x36 part/x18 part|x36 part|x18 part Data allocated for ECC none none 7b 12b 6b 20b 10b (min) Working Data (max) 72b 36b 65b 60b 30b 52b 26b - n/a - Associated Efficiency 100% 90% 83% 72%
Slide 5: Hamming Code Write Logic
Hamming Code Write Logic Bit Position ….. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 P1 P2 D1 P3 D2 D3 D4 P4 D5 D6 D7 D8 D9 D10 D11 P5 D12 D13 D14 D15 D16 D17 D18 Write Data 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 w/o ECC bits ECC P1 0 0 1 0 1 1 1 1 0 0 0 1 ECC P2 0 0 1 0 0 1 0 1 1 0 1
Slide 6: Hamming Code Read Logic
Hamming Code Read Logic Bit Position ….. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Error Code P1 P2 D1 P3 D2 D3 D4 P4 D5 D6 D7 D8 D9 D10 D11 P5 D12 D13 D14 D15 D16 D17 D18 (ECn) Read Data w/ ECC bits 0 0 0 1 1 1 0 0 1 0 1 0 0 0 1 0 0 1 0 1 0 1 1 before correction Check P1 (EC1) 0 0
Slide 7: Multi-Bit Errors
Multi-Bit Errors • Multi-bit errors cannot be detected or corrected. • SRAM architecture substantially reduces multi-bit error probability. Bit Lines Word Lines
Slide 8: ECC Impact on Die Size
ECC Impact on Die Size Single 18Mb/23Mb Memory Quadrant Layouts No ECC Layout ECC Layout Option #1 (rejected) ECC Layout Option #2 (utilized) Die Size = X Die Size = 1.27X Die Size = 1.18X
Slide 9: ECC Impact on Performance
ECC Impact on Performance • Implemented with Dynamic XOR logic. • ~30% faster than Static. • ~20% less power consumption than Static. • Adds ~500ps to total Read Latency.
Slide 10: Test Methodology
Test Methodology Test Methodology Block Diagram 18 18 5 Data D 18 ECC Memory (xor) ECC (xor) WPM (x18) & Write ECn Decoding 0 Error WDM 5 Correction 0 Parity 5 1 18 0 Logic Q 5 5 Memory P1-P5 1 (x5) 1 RPM WPM ECBY Test Mode Function WDM Write Data Memory only WPM Write Parity Memory only RPM Read Pa
Slide 11: SER Cosmic Ray Testing
SER Cosmic Ray Testing • Conducted by iRoC Technologies • Conducted at LANSCE WNR facility in Los Alamos, NM
Slide 12: Accelerated SER Results 65nm 72Mb SigmaQuad/DDR
Accelerated SER Results 65nm 72Mb SigmaQuad/DDR Cosmic Ray FIT Values at Sea Level, New York City Test SEU FIT SBU FIT MCU FIT SEFI FIT SEL FIT Condition ECC Off 567 305 262 0 0 +23/-20% +22/-19% +23/-20% ECC On 0 0 0 0 0 FIT rate values are per Mbit per 109 hours, and represent 95% confidence level
Slide 13: Summary of Benefits
Summary of Benefits 1. Virtually zero SER. 2. 100% utilization of data path for working data. 3. Better efficiency. 4. Simplified controller design / broader controller options.
Slide 14: remo
remo COMMITMENT INNOVATION SPEED