Nxp Semiconductors N.v. · NASDAQ:NXPI
Nxp Semiconductors — Technical Presentation (May 2019)
45 slides from Nxp Semiconductors's technical presentation, May 2019
Slide 1: Advance Your IoT Security Leveraging Hardware Protected Keys
ADVANCE YOUR IOT SECURITY LEVERAGING HARDWARE PROTECTED KEYS DONNIE GARCIA NXP IOT SECURITY SOLUTIONS MAY 2019 PUBLIC
Slide 2: Hardware Protected Keys Webinar Series
Hardware Protected Keys Webinar Series Recording COMPANY PUBLIC 1
Slide 3: Agenda
Agenda • Quick recap and highlights • LPC5500 Series Overview • Security Model & Security Technology • LPC55S6xx Security Technology − Security Subsystem − Arm Trustzone − Secure Debug • LPC5500 PUF based Key Management • Conclusions 2 PUBLIC
Slide 4: Quick Recap & Highlights
QUICK RECAP & HIGHLIGHTS 3 PUBLIC
Slide 5: System Level Requirements
System Level Security Goals Depend on Cryptography System Level Requirements Protect symmetric and Actively monitor physical Update software when Monitor and report Establish a trusted private keys with and logical conditions for vulnerabilities are unauthorized Wireless supply chain hardware intrus
Slide 6: Protected over the lifecycle of the Cryptographic keys
Protected over the lifecycle* of the Cryptographic keys • Key Lifecycle Generation − Generation ▪ Who/what creates the key material − Establishment Establishment ▪ How the key material is shared or signed between entities − Storage Storage ▪ Where the key material is placed for future access − Use ▪
Slide 7: Exploring Protected Key Options
Exploring Protected Key Options NXP IoT Security ICs: • Strongest protection • Provides runtime A71CH across all key life stages Security Hardening on application security A100x Authenticator • Uses: MCU/MPU • Uses: SE050 • Device identity and • Secure boot establishing TLS/onboarding • Bulk data pr
Slide 8: SRAM PUF Overview
SRAM PUF Overview Leverages the intrinsic 1 Process Variation 3 Silicon Fingerprint entropy of the silicon manufacturing process Naturally occurring The start-up values create a variations in the attributes of random and repeatable transistors when chips are pattern that is unique to Device unique,
Slide 9: HW Protected Keys Example: Hardware PUF
HW Protected Keys Example: Hardware PUF Recently launched LPC5500 family also makes use of PUF technology on the microcontroller in addition to other security capabilities 8 PUBLIC
Slide 10: LPC5500 Series Overview
LPC5500 SERIES OVERVIEW 9 PUBLIC
Slide 11: NXP LPC5500 MCU Series Roadmap
NXP LPC5500 MCU SERIES ROADMAP Subject to Change COMMON PLATFORM ARCHITECTURE FOR COMPLETE SCALABILITY AREA & PERFORMANCE EFFICIENT LPC55S8x/8x Common features Rich Graphics across families, Up to 180 MHz Cortex-M33 (dual, PQ) Advanced Up to 1280KB Flash/512KB SRAM • FS USB (wo xtal) Efficiency & Di
Slide 12: LPC55S6x Product Overview
LPC55S6x Product Overview Core Platform Advanced Security Subsystem Core Platform • Up to 100MHz Cortex-M33 • Protected Flash Region (PFR) Timers - TrustZone, MPU, FPU, SIMD • AES-256 HW Encryption/Decryption Engine Arm Cortex-M33 5 x 32b Timers SCTimer/PWM Up to 100 MHz • Up to 100MHz Cortex-M33 •
Slide 13: NXP's LPC5500 Product Spotlight
NXP’s LPC5500 Product Spotlight Bringing Intelligence & Efficiency to the Edge Single & Dual-core Cortex-M33 MCU Series 1 2 • 755 CoreMarks and 32uA/MHz for leading performance efficiency • 10x improvement for signal processing & cryptography • TrustZone + Secure Execution Environment (SEE) • Rich i
Slide 14: LPC5500 MCU Series
NXP LPC5500 MCU SERIES MCUXPRESSO SOFTWARE & TOOLS ECOSYSTEM Complimentary with Extensive Support Hardware Platform for Ease of Development • On-board debug circuit • PCB Layout, Schematic and Board Files Available LPCXpresso55S69: LPC55S69-EVK Simplify secure embedded development; Reduce time to ma
Slide 15: LPC5500 Series Security Resources
LPC5500 Series Security Resources (as of 4/2019) Element14 Secure your Sensor with LPC5500 series Embedded World: LPC5500 Security white paper LPC55S69 Security Solutions for IoT Arm+NXP Webinar on LPC5500 LPC55Sxx usage of the PUF and Hash Crypt to AES coding LPC55S6x Secure GPIO and Usage LPC55Sxx
Slide 16: Security Model & Security Technology
SECURITY MODEL & SECURITY TECHNOLOGY 15 PUBLIC
Slide 17: Security Model
Security Model Policies Threat landscape Methods The rules in place that The definition of the attacks The means by which the identify the data that and attackers that the end policies for the device are should be protected device will face and protect enforced. Involves the against. Considers the a
Slide 18: NXP Solutions for Edge Computing
NXP Solutions for Edge Computing IoT Nodes Edge Gateways Cloud Infrastructure HOME ETHERNET GATEWAY SWITCH Data Machine Analytics Learning WIRELESS INDUSTRIAL ROUTER CONTROLLER Customer Solution App App App Multiple Cloud Frameworks NXP SW Platform NXP SW Platform Thin Middleware Middleware Applicat
Slide 19: NXP Security Technology
NXP Security Technology Documentation & Certifications Manufacturing Secure Security Users Manual Protection Boot App. Notes 8 1 Community Virtualization/ Secure HW Firewalls Storage Software &Tools 7 2 MCUXpresso Code Signing Tools Manufacturing Tools Tamper 6 3 Key Serial Download Tools Detection
Slide 20: LPC55S6x Product Overview
LPC55S6x Product Overview Core Platform • Up to 100MHz Cortex-M33 Advanced Security Subsystem Core Platform Timers - TrustZone, MPU, FPU, SIMD • Protected Flash Region (PFR) Arm Cortex-M33 5 x 32b Timers SCTimer/PWM Up to 100 MHz • Up to 100MHz Cortex-M33 • AES-256 HW Encryption/Decryption Engine Tr
Slide 21: LPC55S6xx Security Technology
LPC55S6XX SECURITY TECHNOLOGY 20 PUBLIC
Slide 22: Security Subsystem Overview
NXP LPC5500 MCU SERIES SECURITY SUBSYSTEM OVERVIEW • ROM supporting − Secure Boot, Debug Authentication & DICE Engine ROM Firmware • TrustZone for Cortex-M33 Debug Authentication Secure Boot DICE Engine − Arm’s Security Attribution Unit (SAU) − Arm’s Memory Protection Unit (MPU): Secure & Non-Secure
Slide 23: Virtualization/Hardware Firewalls
Virtualization/Hardware Firewalls Protect from Software & Remote Attacks Challenges LPC55S69 solution • Protect from software attacks • Based on Cortex-M33 with ARM’s Trustzone technology − Buffer overflow • NXP’s Light weight device attribution unit to − Interrupt/Starvation simplify setup process
Slide 24: Virtualization/Hardware Firewalls
Virtualization/Hardware Firewalls Secure AHB bus matrix Cortex-M33 DMA0 DMA1 other masters SAU • Has Security side band signals − HPRIV, HNONSEC IDAU MSW MSW MSW Secure Multilayer AHB ▪ Pole and anti-pole version of signals used for Matrix C-AHB S-AHB tamper detection MPC Flash Memory PPC • PPC per
Slide 25: Virtualization/Hardware Firewalls: Light weight device attribution
Lightweight Device Arbitration Unit Virtualization/Hardware Firewalls 0xFFFF_FFFF Memory attribution Secure 256MB 0xF000_0000 PPB Non Secure 256MB 0xE000_0000 Secure 256MB 0xD000_0000 Non Secure 256MB NXP’s Light weight device attribution 0xC000_0000 • Secure 256MB 0xB000_0000 unit 0xA000_0000 Non S
Slide 26: Virtualization/Hardware Firewalls: ROM Configuration of TrustZone
Virtualization/Hardware Firewalls ROM Configuration of Trustzone • During boot process Trustzone preset data can be provisioned by the zero stage boot (ROM) − This ensures that before any software runs on the device, TrustZone settings are pre- loaded − This extends the TrustZone protections from th
Slide 27: Virtualization/Hardware Firewalls: Secure GPIO
Virtualization/Hardware Firewalls Secure GPIO • GPIO Read path is always available on a standard microcontroller − Secret data could be accessible from this read path • With Secure GPIO peripheral, when SEC_GPIO_MASK is cleared, the read path from pins is blocked 26 PUBLIC
Slide 28: Secure debug
Secure debug Debug protection mechanism Challenges LPC55S69 Solution • Only authorized external entity allowed to • Supports RSA-2048/RSA-4096 signed debug certificate based challenge response authentication to open debug access • Permit access only to allowed assets • Provides individual debug acce
Slide 29: Secure debug
Secure debug Debug authentication flow 1 Start Debug Mailbox Exchange 2 SYS_RESET_REQ 3 Debug Authentication Start (DBG_AUTH_START) • Create DAC based on DCFG 4 Debug Authentication Challenge (DAC) • Generate 16bytes of random challenge vector • Find matching DC • Sign Challenge vector • Create DAR
Slide 30: Secure debug
Secure debug Debug protection mechanism Debug Credential (DC) Certificate PKI for Secure boot and Debug • Same Root of Trust Private keys are used to create the DC signature • Options for HW and SW constraints − Device Unique ID bound − Level of Debug access − Mass erase enable 29 PUBLIC
Slide 31: Secure Debug
Secure Debug LPC55Sxx Debug Domains – SoC Credential Constraints DC HW Credential Constraints SWCLK Configuration Control NIDEN - Non-secure non-invasive debug. SWDIO TRACECLK TRACEDATA[0-3] • Fields in Customer SWO DBGEN - Non-secure invasive debug Programed Protect Flash SPNIDEN - Secure non-invas
Slide 32: Secure debug: Debug authentication for RMA use case
Secure debug Debug authentication for RMA use case 1• OEM generates RoT key pairs and programs the device before shipping. − SHA256 hash of RoT public key hashes 1 ROTK0Prv • Field Technician generates his own key pair and Ro Ro TK TK 0 1 Ro ROTK0Pub provides public key to OEM for authorization. TK
Slide 33: PUF Based Key Management
PUF BASED KEY MANAGEMENT 32 PUBLIC
Slide 34: Using PUF Technology
Using PUF Technology NO SECRETS STORED ON CHIP SRAM Start-up Pattern SRAM PUF IP AC= AC Helper Data 33 PUBLIC
Slide 35: PUF based Key Management on LPC5500 Series
PUF based Key Management on LPC5500 Series (F) Helper data to allow a device to build its PUF master key which is used to protect other Key Codes Key code for a Key Encryption Key that protects SB2.x files Dedicated space for an AES protected key code 34 PUBLIC
Slide 36: PUF based Key Management on LPC5500 Series
PUF based Key Management on LPC5500 Series (L) Lifecycle management of PUF, block future cryptographic context generation for the device DICE related key code: Trusted Computing Group documentation Dedicated space for PRINCE region key codes (128bit) 35 PUBLIC
Slide 37: Command line or GUI options for PUF provisioning
Command line or GUI options for PUF provisioning Scalable methods for instantiating device unique keys which are protected by PUF technology “Using A1 silicon we are working on enabling support for Untrusted-CM manufacturing. When that happens device unique key store( PUF activation code, Prince key
Slide 38: Challenge: Asset Protection
Challenge: Asset Protection • On-chip non-volatile storage is used for storing important assets − Secret keys − Proprietary SW from OEM and Silicon Manufacturer − Application code − Other sensitive information • Prone to attacks with malicious intent − Reading the code for cloning − Tampering for ▪
Slide 39: PRINCE for encrypted execution
PRINCE for encrypted execution • Is a cryptographic algorithm developed by NXP + 2 Universities − https://eprint.iacr.org/eprint-bin/getfile.pl?entry=2012/529&version=20140612:115014&file=529.pdf • A light-weight symmetric block cryptography algorithm − 64b block cipher, with 128b crypto key − Same
Slide 40: LPC55Sxx Encrypted Flash Regions
LPC55Sxx Encrypted Flash Regions • Data stored in Flash is encrypted version • Supports 3 regions in 640KB Flash 0x9FFFFF Region-2 − Each region is be at 256KB Address boundary 128KB 0x80000 − Allows multiple code images from independent source to co-exist Region-1 − Secret-Key and IV Pair per regio
Slide 41: Hardware Protected Keys Webinar Series
Hardware Protected Keys Webinar Series Recording 40 PUBLIC
Slide 42: Conclusion
CONCLUSION 41 PUBLIC
Slide 43: Summary
Summary • LPC55S69 provides rich peripheral interfaces and security features needed for todays IoT applications. − PUF based key protection − ROM enabled key management • Arm Trustzone for cortex-M enhances protection from scalable remote attacks − Enforced for the CPU and the SoC microarchitecture
Slide 44: Summary
Summary • LPC55S69 provides rich peripheral interfaces and security features needed for todays IoT applications. − PUF based key protection − ROM enabled key management • Arm Trustzone for cortex-M enhances protection from scalable remote attacks − Enforced for the CPU and the SoC microarchitecture
Slide 45: NXP trademarks notice
NXP and the NXP logo are trademarks of NXP B.V. All other product or service names are the property of their respective owners. © 2018 NXP B.V.
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