Enablence Technologies Inc. · TSXV:ENA

Enablence Technologies — Technical Presentation (June 2023)

29 slides from Enablence Technologies's technical presentation, Jun 13, 2023

  1. Slide 1: Advances in machine learning-based design for high-volume manufacturing of planar lightwave circuits

    Advances in machine learning-based design for high-volume manufacturing of planar lightwave circuits S. Bidnyk, K. Yadav, A. Balakrishnan Enablence Technologies Inc. Photonics North June 13, 2023

  2. Slide 2: Introduction: PLC Technology

    Introduction PLC Technology • Integrated photonics has emerged as a key technology to enable advancements in high-speed communication and advanced vision systems. • Photonic integrated circuits possess high optical performance and are well suited for both monolithic and hybrid integration in a compa

  3. Slide 3: Introduction: Silica-on-silicon PLC platform

    Introduction Silica-on-silicon PLC platform • A versatile and low-cost platform with powerful characteristics. • Widespread applications, including high-speed communication, medical imaging, autonomous driving, and environmental sensing. 3

  4. Slide 4: Our PLC Platform

    Our PLC Platform Silica-on-silicon • Buried silica-based waveguides with a Δn = 2.0% Δn = 2.0% refractive index contrast and typical waveguide dimensions of 3 ⨉ 3 μm. SiO2 • Fabricated using atmospheric pressure core chemical-vapor deposition (APCVD) and SiO2 reactive ion etching. cladding • We offe

  5. Slide 5: Ultra-dense architectures: Long delay lines

    Ultra-dense architectures Long delay lines • An example of a 10-meter-long spiral with waveguide density close to the theoreUcal limit: 10 mm • Realized in silica-on-silicon with a refractive index contrast of Δn = 2.0%. • Total device footprint: 1.0 cm2 • Waveguide density close to the theoretical

  6. Slide 6: Ultra-dense architectures: 4-channel CWDM multiplexer

    Ultra-dense architectures 4-channel CWDM multiplexer • Total device footprint: 0.18 cm2 • Worst-channel insertion loss of 1.5 dB • Without the two fiber couplings, on-chip loss estimated at 0.3 dB • 1 dB bandwidth of 16.4 nm (>82% of the channel pitch) • Worst case crosstalk of 19 dB • Polarization-

  7. Slide 7: Ultra-dense architectures: 8-channel LAN-WDM multiplexer

    Ultra-dense architectures 8-channel LAN-WDM multiplexer • Total device footprint: 0.38 cm2 • On-chip loss estimated at 0.3 - 0.5 dB • 1 dB bandwidth of 3.5 nm (80% of the channel pitch) • Polarization-independent operation across the O-band (polarization dependent loss < 0.2 dB) 1 2 3 4 6 7 8 9 7

  8. Slide 8: Machine-driven design

    Machine-driven design Progressive abstraction of complexity STEP 1: Simplified functional view I0 WG0 WG0 F10 WG0 L1,L4 WG0 L1,L4 F30 WG0 L1 WG6 L0 WG6 L0 WG1 L4 WG0 L1 WG0 L1 I1 WG2 L0-L7 F0 WG2 WG2 L3,L6F2 WG2 L2,L5 F31 WG2 L2 WG3 L5 WG1 L4 WG2 L2 WG2 L2 WG4 L3 I2 WG4 WG4 F11 WG4 L2,L5 WG4L3,L6 F3

  9. Slide 9: ML-driven design

    ML-driven design Building custom models Leveraging ML technologies: • Adopt Keras API for arbitrary advanced workflows • Build on top of TensorFlow 2 • Deploy on AWS 9

  10. Slide 10: Advanced vision

    Advanced vision Optical processing COHERENT FEATURE EXTRACTION f1 f2 f3 f4 f5 PDs spatial distance … 3D imaging velocity vector OPTICAL PROCESSING tissue density spectral analysis layer metrology surface texture DSP molecular detection antibody bindings Aφ λ P LD art conservation medical diagnostics

  11. Slide 11: Optical building blocks: Polarization beam splitters

    Optical building blocks Polarization beam splitters composite coupler birefringent region composite coupler • Polarization isolation > 22 dB over 1510 – 1575 nm measurement range • Highly-integrated arrayed PBS solution for LiDAR applications

  12. Slide 12: Optical building blocks: k-clocks for OCT and LiDAR

    Op9cal building blocks k-clocks for OCT and LiDAR • Swept-source OCT (SS-OCT) and FMCW LiDAR measure the signal in k-space, which is linear to the change in the optical frequency of the swept source. • k-clock is a timing control signal that is produced by an auxiliary MZI that is used as a highly l

  13. Slide 13: PLCs in Production: Challenges in high volumes

    PLCs in Production Challenges in high volumes • To achieve high-performing devices, we rely on advanced data analysis that is tightly coupled to our design and fabrication. • We use machine learning (ML) algorithms to scale the capabilities of the silica-on-silicon PLC platform to high-volume manufa

  14. Slide 14: Design optimizations: The challenge of process uniformity

    Design optimizations The challenge of process uniformity • Process uniformity and consistency is criUcal in the manufacturing of photonic chips. • TradiUonally, standard staUsUcal methods are used to compensate for systemaUc process non-uniformiUes: systematic index variation 14

  15. Slide 15: Design Optimizations: Adjustments through ML

    Design Optimizations Adjustments of design parameters through ML TRAINING SET INPUT x(i) LABEL d(i) ◼ ✿ ⬤ ⏣ ✦ ✚ ⌘ ★ ⌽ ► ▲ ♠ ❖ ⌾ ◀ ⚑ ♣ ♦ MODEL TRAINING simulated spectrum design parameters VALIDATION SET MODEL VALIDATION 15

  16. Slide 16: Design Optimizations: Adjustments through ML

    Design Optimizations Adjustments of design parameters through ML INPUT x(i) d#(i) ◼ ✿ ⬤ ⏣ TRAINED ✦ ✚ ⌘ ★ MODEL ⌽ ► ▲ ♠ ❖ ⌾ ◀ ⚑ ♣ ♦ measured inferred design spectrum parameters 16

  17. Slide 17: Design Optimizations: Adjustments through ML

    Design Optimizations Adjustments of design parameters through ML Ini:al ML-enhanced mask mask INPUT x(i) d#(i) ◼ ✿ ⬤ ⏣ TRAINED ✦ ✚ ⌘ ★ MODEL ⌽ ► ▲ ♠ ❖ ⌾ ◀ ⚑ ♣ ♦ measured inferred design spectrum parameters 17

  18. Slide 18: Design Optimizations: Adjustments through ML

    Design Op9miza9ons Adjustments of design parameters through ML • To validate the approach, we applied it to a production mask with 600 devices: • Devices on the mask were designed to be identical, except for a refractive index distribution correction computed by traditional statistical means. • Desp

  19. Slide 19: Design Optimizations: Adjustments through ML

    Design Optimizations Adjustments of design parameters through ML • To validate the approach, we applied it to a producUon mask with 600 devices: • We used the model predicDons to insert correcDons into each of the chips on the mask, thereby producing a ML-enhanced version of the producDon mask. Init

  20. Slide 20: Performance Predictions

    Performance Predic9ons Classifica?on based on a wafer probe measurement 20

  21. Slide 21: Performance Predictions

    Performance Predictions Classification based on a wafer probe measurement Probed locations on the wafer 21

  22. Slide 22: Performance Predictions

    Performance Predic9ons Classifica?on based on a wafer probe measurement Probed loca2ons Typical spectroscopic on the wafer signature 22

  23. Slide 23: Performance Predictions

    Performance Predic9ons Classifica?on based on a wafer probe measurement Probed loca2ons Typical spectroscopic Predicted performance of on the wafer signature hundreds of chips on a wafer 23

  24. Slide 24: Performance Predictions

    Performance Predictions Classification based on a wafer probe measurement Specification parameters: 1. IL 2. IL uniformity 3. Grid detuning 4. Channel spacing uniformity 5. 0.5 dB passband 6. 1 dB passband 7. 3 dB passband 8. PDL 9. Ripple 10. Adjacent crosstalk 11. Non-adjacent crosstalk 12. Total

  25. Slide 25: Performance Predictions

    Performance Predictions Classification based on a wafer probe measurement Tradi&onal chip tes&ng Wafer probe tes&ng Time to measure a 4-channel chip 2 minutes Time to perform a wafer probe measurement 12 minutes Cost of measuring a 4-channel chip (North America) $4.25 Time to infer the PASS/FAIL of

  26. Slide 26: Performance Predictions

    Performance Predictions Classification based on a wafer probe measurement Predicted PASS/FAIL over 26 specification parameters 26

  27. Slide 27: Performance Predictions

    Performance Predictions Classification based on a wafer probe measurement Predicted PASS/FAIL Actual PASS/FAIL over 26 specification over 26 specification parameters parameters 27

  28. Slide 28: Conclusions

    Conclusions • We described how AI/ML revolutionized the way photonic integrated circuits are designed and fabricated in a high-volume environment: • The automated layout transformers overcome the complexity of design and physical layer layout enabling novel architectures not only in communications b

  29. Slide 29: Tutorial – Ksenia Yadav

    Tutorial 2 – Ksenia Yadav Machine Learning Fundamentals with Applications in Photonics, Wed, June 14, 11:05 – 12:05, ROOM 513 29

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