Analog Devices, Inc. · NASDAQ:ADI
Analog Devices — Technical Presentation (December 2008)
61 slides from Analog Devices's technical presentation, December 2008
Slide 1: Performance Tuning on the Blackfin Processor
Performance Tuning on the Blackfin Processor 1
Slide 2: Outline
Outline Introduction Building a Framework Memory Considerations Benchmarks Managing Shared Resources Interrupt Management An Example Summary 2
Slide 3: Introduction
Introduction The first level of optimization is provided by the compiler The remaining portion of the optimization comes from techniques performed at the “system” level z Memory management z DMA management z Interrupt management The purpose of this presentation is to help you understand how so
Slide 4: One Challenge
One Challenge How do we get from here Type of Memory Required For Total Direct Format Columns Rows Pixels Implementation SQCIF 128 96 12288 L1, L2, off-chip L2 QCIF 176 144 25344 L1, L2, off-chip L2 Unlimited memory CIF 352 288 101376 L2, off-chip L2 Unlimited processing VGA 640 480 307200 off-chip
Slide 5: Processor Utilization
The path to optimization Compiler System Assembly Optimization Optimization Optimization 100.00% 90.00% let compiler optimize 80.00% 70.00% Processor Utilization 60.00% 50.00% exploit architecture features 40.00% 30.00% efficient memory layout 20.00% use specialized instructions 10.00% streamline da
Slide 6: Creating a Framework
The World Leader in High Performance Signal Processing Solutions Creating a Framework
Slide 7: The Importance of Creating a “Framework”
The Importance of Creating a “Framework” Framework definition: The software infrastructure that moves code and data within an embedded system Building this early on in your development can pay big dividends There are three categories of frameworks that we see consistently from Blackfin develop
Slide 8: Common Frameworks
Common Frameworks Processing on the fly z Safety-critical applications (e.g., automotive lane departure warning system) z Applications without external memory Programming ease overrides performance z Programmers who need to meet a deadline Performance supersedes programming ease z Algorithms t
Slide 9: Processing on the fly
Processing on the fly Can’t afford to wait until large video buffers filled in external memory Instead, they can be brought into on-chip memory immediately and processed line-by-line z This approach can lead to quick results in decision-based systems The processor core can directly access line
Slide 10: Example of “Processing-on-the-fly” Framework
Example of “Processing-on-the-fly” Framework Collision avoidance CORE Single cycle Collision Warning 720 pixels access Video in 480 pixels DMA L1 MEM 33 msec frame rate 63 µsec line rate Data is processed one line at a time instead of waiting for an entire frame to be collected. 10
Slide 11: “Programming Ease Rules”
“Programming Ease Rules” Strives to achieve simplest programming model at the expense of some performance Focus is on time-to-market z Optimization isn’t as important as time-to-market It can always be revisited later z Provides a nice path for upgrades! Easier to develop for both novices an
Slide 12: Example of “Programming Ease Rules” framework
Example of “Programming Ease Rules” framework Cores split Data CORE CORE processing Processed Data DMA Sub-image External Memory L2 MEM DMA Video in DMA This programming model best matches time-to-market focused designs 12
Slide 13: “Performance Rules”
“Performance Rules” Bandwidth-efficient Strives to attain best performance, even if programming model is more complex z Might include targeted assembly routines Every aspect of data flow is carefully planned Allows use of less expensive processors because the device is “right-sized” for the
Slide 14: Example of “Performance Rules” Framework
Example of “Performance Rules” Framework CORE CORE Single cycle Single cycle Compressed access access data DMA Macro block External Memory L1 MEM L1 MEM DMA Video in DMA 1 line at a time L2 MEM Provides most efficient use of external memory bus. 14
Slide 15: Common Attributes of Each Model
Common Attributes of Each Model Instruction and data management is best done up front in the project Small amounts of planning can save headaches later on 15
Slide 16: Features that can be used to improve performance
The World Leader in High Performance Signal Processing Solutions Features that can be used to improve performance
Slide 17: Now that we have discussed the background…
Now that we have discussed the background… We will now review the concepts that will help you tune performance z Using Cache and DMA z Managing memory z Managing DMA channels z Managing interrupts 17
Slide 18: Cache vs. DMA
The World Leader in High Performance Signal Processing Solutions Cache vs. DMA
Slide 19: Cache versus DMA
19 DMA OMA Cache Programmers may find a combination is best _- Performance ~~ Ease of Use ~ Lal DEVICES
Slide 20: Cache
The World Leader in High Performance Signal Processing Solutions Cache
Slide 21: Configuring internal instruction memory as cache
Configuring internal instruction memory as cache foo1(); Core Way 1 foo2(); foo3(); External memory Example: L1 instruction memory configured as 4-way set-associative cache Instructions are brought into internal memory where single cycle performance can be achieved Instruction cache provides several
Slide 22: Configuring internal data memory as cache
Configuring internal data memory as cache Volatile data Peripheral Way 1 DMA Core Static data Cache External memory Example: Data brought in from a peripheral Data cache also provides a way to increase performance Usually provides the highest bandwidth path into the core z For linear data, the n
Slide 23: Write-back vs. Write-through
Write-back vs. Write-through Write-back is usually 10-15% more efficient but … z It is algorithm dependent Write-through is better when coherency between more than one resource is required Make sure you try both options when all of your peripherals are running 23
Slide 24: DMA
The World Leader in High Performance Signal Processing Solutions DMA
Slide 25: Why Use a DMA Controller?
Why Use a DMA Controller? The DMA controller runs independently of the core z The core should only have to set up the DMA and respond to interrupts Core processor cycles are available for processing data DMA can allow creative data movement and “filtering” z Saves potential core passes to re-a
Slide 26: Using 2D DMA to efficiently move image data
Using 2D DMA to efficiently move image data 26
Slide 27: DMA and Data Cache Coherence
DMA and Data Cache Coherence Coherency between data cache and buffer filled via DMA transfer must be maintained Cache must be “invalidated” to ensure “old” data is not used when processing most recent buffer z Invalidate buffer addresses or actual cache line, depending on size of the buffer In
Slide 28: Instruction partitioning
Does code fit into internal memory? Yes No Instruction partitioning Map code Map code to into internal external memory memory Desired performance is Turn Cache on achieved No Is desired performance achieved? Lock lines with critical code Use L1 SRAM Yes Is desired performance achieved? Yes No Use ov
Slide 29: Data partitioning
Is the data volatile or static? Static Volatile Map to cacheable Will the buffers fit into Data partitioning memory internal memory? locations Yes No Single cycle access achieved Map to external memory Is DMA part of the programming model? No Turn data cache on Desired performance is achieved Is buf
Slide 30: A Combination of Cache and DMA Usually Provides the Best Performance
A Combination of Cache and DMA Usually Provides the Best Performance Instruction Cache Func_A Way 1 Func_B Once cache is Way 2 enabled and the High bandwidth cache fill Func_C DMA controller is Way 3 configured, the programmer can Way 4 Func_D focus on core algorithm Data Cache Func_E development. W
Slide 31: Memory Considerations
The World Leader in High Performance Signal Processing Solutions Memory Considerations
Slide 32: Blackfin Memory Architecture: The Basics
Blackfin Memory Architecture: The Basics Core 600MHz Configurable as Cache or SRAM Single cycle to L1 Instruction L1 Data Memory L1 Data Memory access Memory 600MHz 10’s of Kbytes Unified 300MHz Several cycles to access DMA on-chip L2 100’s of Kbytes On-chip Off-chip Several system cycles to access
Slide 33: Instruction and Data Fetches
Instruction and Data Fetches In a single core clock cycle, the processor can perform z One instruction fetch of 64 bits and either … z Two 32-bit data fetches or z One 32-bit data fetch and one 32-bit data store The DMA controller can also be running in parallel with the core without any “cycle
Slide 34: Partitioning Data – Internal Memory Sub-Banks
Partitioning Data – Internal Memory Sub-Banks Multiple accesses can be made to different internal sub-banks in the same cycle Core fetch DMA Core fetch Buffer0 Buffer0 Buffer1 DMA Buffer2 Buffer1 DMA Coefficients Core fetch DMA DMA Buffer2 Unused Core fetch Coefficients Unused Un-optimized Optimiz
Slide 35: L1 Instruction Memory 16KB Configurable Bank
L1 Instruction Memory 16KB Configurable Bank 4KB 4KB sub-bank sub-bank EAB – Cache Line Fill DCB - DMA Instruction 4KB 4KB sub-bank sub-bank 16 KB SRAM 16 KB cache • Four 4KB single-ported • Least Recently Used sub-banks replacement keeps frequently executed code in cache • Allows simultaneous • 4-w
Slide 36: L1 Data Memory 16KB Configurable Bank
L1 Data Memory 16KB Configurable Bank Block is Multi-ported when: Accessing different sub-bank 4KB 4KB OR sub-bank sub-bank Accessing one odd and one even EAB – Cache Line Fill access (Addr bit 2 different) within the same sub-bank. DCB Data 0 - DMA Data 1 4KB 4KB sub-bank sub-bank • When Used as SR
Slide 37: Partitioning Code and Data -- External Memory Banks
Partitioning Code and Data -- External Memory Banks Row activation within an SDRAM consumes multiple system clock cycles Multiple rows can be “active” at the same time z One row in each bank Code Code Video Frame 0 Instruction Instruction Fetch Video Frame 1 Video Frame 0 Fetch Four External Ref
Slide 38: Benchmarks
The World Leader in High Performance Signal Processing Solutions Benchmarks
Slide 39: Important Benchmarks
Important Benchmarks Core accesses to SDRAM take longer than accesses made by the DMA controller z For example, Blackfin Processors with a 16-bit external bus behave as follows: 16-bit core reads take 8 System Clock (SCLK) cycles 32-bit core reads take 9 System Clock cycles 16-bit DMA reads tak
Slide 40: Managing Shared Resources
The World Leader in High Performance Signal Processing Solutions Managing Shared Resources
Slide 41: External Memory Interface: ADSP-BF561
External Memory Interface: ADSP-BF561 Core has priority to external bus You are able to program this so unless that the DMA has a higher DMA is urgent* priority than the core * “Urgent” DMA implies data will be lost if access isn’t granted Core A is higher priority than Core B Programmable priority
Slide 42: Priority of Core Accesses and the DMA Controller at the External Bus
Priority of Core Accesses and the DMA Controller at the External Bus A bit within the EBIU_AMGCTL register can be used to change the priority between core accesses and the DMA controller 42
Slide 43: What is an “urgent” condition?
What is an “urgent” condition? Peripheral Peripheral When the DMA FIFO is empty and the Peripheral is transmitting Peripheral Peripheral When the DMA FIFO is full and the FIFO or FIFO Peripheral has a sample to send DMA FIFO DMA FIFO Empty Full External memory External memory 43
Slide 44: Bus Arbitration Guideline Summary: Who wins?
Bus Arbitration Guideline Summary: Who wins? External memory (in descending priority) z Locked Core accesses (testset instruction) z Urgent DMA z Cache-line fill z Core accesses z DMA accesses We can set all DMA’s to be urgent, which will elevate the priority of all DMAs above Core accesses L1
Slide 45: Tuning Performance
The World Leader in High Performance Signal Processing Solutions Tuning Performance
Slide 46: Managing External Memory
Managing External Memory Transfers in the same direction are more efficient than intermixed accesses in different directions DMA External External Bus Memory Core Group transfers in the same direction to reduce number of turn-arounds 46
Slide 47: Improving Performance
Improving Performance DMA Traffic Control improves system performance when multiple DMAs are ongoing (typical system) z Multiple DMA accesses can be done in the same “direction” For example, into SDRAM or out of SDRAM z Makes more efficient use of SDRAM 47
Slide 48: DMA Traffic Control
DMA Traffic Control DEB_Traffic_Period has the biggest impact on improving performance The correct value is application dependent but if 3 or less DMA channels are active at any one time, a larger value (15) of DEB_Traffic_Period is usually better. When more than 3 channels are active, a value close
Slide 49: Priority of DMAs
The World Leader in High Performance Signal Processing Solutions Priority of DMAs
Slide 50: Priority of DMA Channels
Priority of DMA Channels Each DMA controller has multiple channels If more than one DMA channel tries to access the controller, the highest priority channel wins The DMA channels are programmable in priority When more than one DMA controller is present, the priority of arbitration is program
Slide 51: Interrupt Processing
51 Interrupt Processing ANALOG DEVICES
Slide 52: Common Mistakes with Interrupts
Common Mistakes with Interrupts Spending too much time in an interrupt service routine prevents other critical code from executing z From an architecture standpoint, interrupts are disabled once an interrupt is serviced Higher priority interrupts are enabled once the return address (RETI registe
Slide 53: Programmer Options
Programmer Options Program the most important interrupts as the highest priority Use nesting to ensure higher priority interrupts are not locked out by lower priority events Use the Call-back manager provided with System Services z Interrupts are serviced quickly and higher priority interrupts
Slide 54: A Example
The World Leader in High Performance Signal Processing Solutions A Example
Slide 55: Video Decoder Budget
Video Decoder Budget What’s the cycle budget for real-time decoding? (Cycle/pel * pixel/frame * frame/sec) < core frequency ⇒ Cycle/pel < (core frequency / [pixel/frame * frame/sec]) ⇒ Leave at least 10% of the MIPS for other things (audio, system, transport layers…) For D-1 video: 720x480, 30 fra
Slide 56: Video Decoders
Video Decoders Packet Buffer Ref Frames Display Frames Input Bitstream 1011001001… External Memory •Decode •Interpolation •Uncompensate •Format Conversion Signal processing Internal L1 Memory 56
Slide 57: Data Placement
Data Placement ¾Large buffers go in SDRAM •Packet Buffer (~ 3 MB) •4 Reference Frames (each 720x480x1.5 bytes) •8 Display Frames (each 1716x525 bytes) ¾Small Buffers go in L1 memory •VLD Lookup Tables •Inverse Quantization, DCT, zig-zag, etc. •Temporary Result Buffers 57
Slide 58: Data Movement (SDRAM to L1)
Data Movement (SDRAM to L1) ¾Reference Frames are 2D in SDRAM ¾Reference Windows are linear in L1 Y U V 2D-to-1D DMA used to bring in reference windows for interpolation SDRAM L1 58
Slide 59: Data Movement (L1 to SDRAM)
Data Movement (L1 to SDRAM) ¾All temporary results in L1 buffers are stored linearly. ¾All data brought in from SDRAM are used linearly. Decoded Macroblock L1 SDRAM 1D-to-2D DMA transfers decoded macroblock to SDRAM to build reference 59 frame.
Slide 60: Bandwidth Used by DMA
Bandwidth Used by DMA Input Data Stream 1 MB/s Reference Data In 30 MB/s In Loop Filter Data In 15 MB/s Reference Data Out 15 MB/s In Loop Filter Data Out 15 MB/s Video Data Out 27 MB/s •Calculations based on 30 frames per second. Be careful not to simply add up the bandwidths! Shared resources, bus
Slide 61: Summary
Summary The compiler provides the first level of optimization There are some straightforward steps you can take up front in your development which will save you time Blackfin Processors have lots of features that help you achieve your desired performance level Thank you 61
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