Analog Devices, Inc. · NASDAQ:ADI

Analog Devices — Technical Presentation (May 2024)

97 slides from Analog Devices's technical presentation, May 30, 2024

Slide 1: Stability Analysis of Voltage Feedback Opamps
Stability Analysis of Voltage Feedback Opamps Ed Mullins, Principal Applications Engineer Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved.
Slide 2: Agenda
Agenda ► Review of Bode Plots  Magnitude and Phase Response ► Opamp Gain and Phase  Ideal, Actual ► Voltage Feedback Model  Definitions, Analysis of Closed Loop Gain, Stability Criteria, Rate of Closure ► KWIK Quiz ► Examples  Putting it all together, Examples (Inverting Amplifier, Transimpedanc
Slide 3: Acronyms Used In this Training
Acronyms Used In this Training ► UFG – Unity Gain Frequency, this si where the opamps open loop gain crosses 0dB ► GBP – Gain Bandwidth Product, a constant for voltage feedback opamps, is the product of the gain and frequency at any point on the open loop gain curve ► fZ – Zero frequency in the non-
Slide 4: Acronyms Used In this Training
Acronyms Used In this Training ► CPHOTO – junction capacitance of a photodiode at zero bias voltage ► CCM – common-mode input capacitance of an opamp, can be found in the data sheet ► CDIFF – differential input capacitance of an opamp, can be found in the data sheet Analog Devices Confidential Infor
Slide 5: Bode Plot Review
Bode Plot Review Rule of Thumb - 3dB and 45° of phase shift occurs at each pole frequency -20dB/decade slope 1 f3dB = 2π RC -20dB/decade slope Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 5
Slide 6: Bode Plot Review
Bode Plot Review Rule of Thumb 0° phase shift occurs one decade before and 90° occurs one decade after the pole frequency 1 f3dB = 2π RC -20dB/decade slope ~6° of phase shift one decade before the pole ~84° of phase shift one decade frequency before the pole frequency Analog Devices Confidential Inf
Slide 7: Let’s Add a Second Pole
Let’s Add a Second Pole Rules of Thumb 45° of phase shift at each pole frequency 0° phase shift one decade before the pole frequency 90° of additional phase shift one decade after each pole frequency -20dB/decade slope -40dB/decade slope Notice that 180° phase shift is associated with a two-pole sys
Slide 8: Analysis by Inspection
Analysis by Inspection Slope = 0dB/decade Slope = -20dB/decade 135° 0° phase phase 180° shift shift 45° phase phase 90° shift shift phase shift Slope = -40dB/decade Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 8
Slide 9: Ideal 1st Order Open Loop Gain
Ideal 1st Order Open Loop Gain Gain Phase (dB) Gain (degrees) Phase margin definition: -20dB/dec Inverting 180° First consider this: When applying negative terminal feedback, if the phase shift through the Phase Shift system approaches 180°, it is like the system Phase 90° has positive feedback and
Slide 10: Actual Open Loop Gain
Actual Open Loop Gain Gain Phase (dB) Gain (degrees) Inverting terminal Phase margin from higher Phase Shift order poles occurs after the Phase unity gain crossover and Phase Margin reduces the phase margin at crossover Phase Margin Frequency (Hz) Higher order Unity gain poles crossover Rules of Thu
Slide 11: Voltage Feedback Model
Voltage Feedback Model Definitions A = AOL = Open Loop Gain VERROR VIN A VOUT β = Amount of output fed back to the input ACL = Closed Loop Gain Aβ = Loop Gain β * VOUT 1 β = Ideal Closed Loop Gain β ► Key point: This block diagram model is the basis for VOUT VERROR × A = stability and loop gain anal
Slide 12: Ideal Closed Loop Gain
Ideal Closed Loop Gain Let’s determine the ideal closed loop gain when the opamp is assumed to be ideal with infinite open loop gain: RG RF VOUT VIN A ∞ 1 RF 1 ACL = lim = ACL = 1+ = ACL = (1 + Aβ ) A→∞ 1 + ∞β β RG β Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights rese
Slide 13: Stability Criteria
Stability Criteria Aβ = −1 A A A Aβ 1  180° = ACL = lim A CL = = =∞ (1 + Aβ ) Aβ →−1 1 + (−1) 0 1 =A  180° β Rule of Thumb To determine the stability of the amplifier circuit, plot the Aol and Acl and look at the phase margin at their intercept Analog Devices Confidential Information. ©2021 Analog
Slide 14: Rate of Closure
Rate of Closure Rate of closure indicates phase shift Rules of Thumb Phase margin goes hand in hand with the rate of closure between the AOL and ACL curves To determine the stability of the amplifier circuit, plot the Aol and Acl and look at the phase margin (rate of closure) at their intercept If t
Slide 15: Quiz
Quiz Open Loop Gain ► What is the slope from 10Hz to 1kHz? ► Phase shift at 100Hz? ► What is DC Open Loop Gain in V/V? ► What is the slope from 1kHz to 1MHz? ► Phase shift at 1kHz? ► What is GBP at 40dB? ► What is the slope from 1MHz to 100MHz? ► Phase shift at 10kHz? ► What is UGF? ► Phase shift at
Slide 16: Rate of Closure
Rate of Closure A single pole system has a slope of -20dB/decade with a total of 90° of phase shift A two pole system has a slope of -40dB/decade with a total of 180° of phase shift If a system has a 20dB/dec rate of closure it is stable If a system has a 40dB/dec rate of closure it is unstable Rate
Slide 17: 90° Phase Margin
90° Phase Margin Visual relationships between magnitude response, phase VIN- response and transient response for VOUT VIN+ a unity gain follower modelled with with a second order behavior AC 90°  looks like an RC response T 140 T 120 150m 100 80 Gain (dB) 60 100m 40 20 Voltage (V) 0 -20 50m 180 135
Slide 18: 70° Phase Margin
70° Phase Margin Visual relationships between magnitude response, phase VIN- response and transient response for VOUT VIN+ a unity gain follower modelled with with a second order behavior AC 70°  is ~critically damped T 150m 100m Voltage (V) 50m 0 -50m 0 10u 20u 30u Time (s) Analog Devices Confiden
Slide 19: 45° Phase Margin
45° Phase Margin Visual relationships between magnitude response, phase VIN- response and transient response for VOUT VIN+ a unity gain follower modelled with with a second order behavior AC 45°  One or two visible “bumps” T 140 T 120 150m 100 80 Gain (dB) 60 100m 40 20 Voltage (V) 0 -20 50m 180 13
Slide 20: 25° Phase Margin
25° Phase Margin Visual relationships between magnitude response, phase VIN- response and transient response for VOUT VIN+ a unity gain follower modelled with with a second order behavior AC 25° Decaying oscillations T 140 T 120 150m 100 80 Gain (dB) 60 100m 40 20 Voltage (V) 0 -20 50m 180 135 Phas
Slide 21: Putting it All Together
Putting it All Together 1. Sketch the open loop gain (Aol) vs frequency (data is usually available in the device data sheet) 2. On the same plot, sketch the ideal closed loop gain (1/β) vs frequency (requires a quick intuitive analysis) 3. Observe the Rate of Closure at the intersection of the close
Slide 22: Example Circuit 1: Analyze by Hand
Example Circuit 1: Analyze by Hand AOL ACL Why is the closed loop gain 6dB? Stable or Unstable? Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 22
Slide 23: Example Circuit 1: Analyze Using Simulation
Example Circuit 1: Analyze Using Simulation 1/β AOL Rate of closure is 20dB/dec => Stable Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 23
Slide 25: Example Circuit 2: Transimpedance Amplifier
Example Circuit 2: Transimpedance Amplifier Our opamp seems stable, what could possibly go wrong? Let’s build a photodiode amplifier! Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 25
Slide 26: Example Circuit 2: Transimpedance Amplifier
Example Circuit 2: Transimpedance Amplifier Hmmm! Not stable in the application! Let’s have a look under the hood… Photocurrent Output fOSC = 50kHz Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 26
Slide 27: Example Circuit 2: Transimpedance Amplifier
Example Circuit 2: Transimpedance Amplifier Photodiode Common-mode capacitance capacitance at zero of the opamp bias Common-mode Differential capacitance of the capacitance of Simplify your analysis by lumping opamp the opamp all the capacitances together (note: this capacitance is not relevant as i
Slide 28: Example Circuit 2: Transimpedance Amplifier
Example Circuit 2: Transimpedance Amplifier -20 dB/dec AOL and ACL A = 1 + ZZ CL F 20 dB/dec intercept at Z = R G F F 50kHz! Z = G 1 2π fCIN Rate of closure = ACL lim = 1 f →0 40db/dec ACL lim = ∞ Ideal closed f →∞ unstable loop gain (1/β) =fZ = 1 1 = 205 Hz 2π RF CIN 2π ×10 M Ω × 77.5 pf f Z @ 205
Slide 29: Example Circuit 2: Transimpedance Amplifier
Example Circuit 2: Transimpedance Amplifier Solution: 1 CF = = 1.59 pf Change rate of closure 2π fRF by adding a capacitor in parallel with RF to flatten the gain at high frequency Now the rate of closure is 20 dB/dec and the circuit is stable 1) Add a capacitor in parallel with the feedback resisto
Slide 30: Example Circuit 2: Transimpedance Amplifier
Example Circuit 2: Transimpedance Amplifier Result: The compensated circuit is very stable Notice that the bandwidth of the circuit is determined by RF//CF Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 30
Slide 31: Example Circuit 2: Transimpedance Amplifier
Example Circuit 2: Transimpedance Amplifier For maximum bandwidth while still maintaining 45° of phase margin use the following equations to determine CF: fCOMP = f Z fU 1 fZ = (CIN includes photodiode capacitance, input capacitance of opamp and any PCB parasitics) 2π RF CIN fU = unity gain frequenc
Slide 32: Rule of Thumb - Increasing Cin
Rule of Thumb - Increasing Cin T 140 120 100 80 Gain (dB) 60 Cin increasing 40 20 0 -20 -40 100m 1 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) Keeping RF and the Opamp bandwidth constant, increasing CIN will reduce the zero frequency, increasing the likelihood of stability issues Analog Devices Co
Slide 33: Rule of Thumb - Increasing Opamp BW
Rule of Thumb - Increasing Opamp BW T 140 120 100 80 Increasing Unity Gain Crossover Gain (dB) 60 40 20 0 -20 -40 100m 1 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) Keeping RF and CIN constant, increasing the Opamp bandwidth will bring the zero frequency inside the open loop gain curve, increasing
Slide 34: Rule of Thumb - Increasing RF
Rule of Thumb - Increasing RF T 140 120 100 80 Gain (dB) 60 40 Increasing Rf 20 0 -20 -40 100m 1 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) Keeping CIN and the Opamp bandwidth constant, increasing RF will reduce the zero frequency, increasing the likelihood of stability issues Analog Devices Conf
Slide 35: Rule of Thumb - Increasing Cf
Rule of Thumb - Increasing Cf T 140 120 100 Increasing Cf 80 Gain (dB) 60 40 20 0 -20 -40 100m 1 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) Keeping CIN, RF and the Opamp bandwidth constant, increasing CF will bring the pole frequency inside the open loop gain curve, improving the stability of the
Slide 36: Key Lessons Learned
Key Lessons Learned ► Input capacitance (on the inverting input) reacts with feedback resistance to create a pole in the feedback (same as adding a zero in the closed loop gain (1/β)) and reduces the circuit phase margin ► Large value feedback resistors react with the input capacitance at lower freq
Slide 38: Simulating for Stability
Simulating for Stability ► You must break the loop and simulate in the AC domain ► During an “AC” analysis the operating point is first determined, then the circuit is linearized around that operating point, basically think about it as the simulator is taking the tangent to the curve (see curve belo
Slide 39: Simulating for Stability
Simulating for Stability Equivalent circuit at DC Equivalent circuit at frequencies above DC Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 39
Slide 40: Simulating for Stability
Simulating for Stability ► Label the amplifier output “AB”…this is also known as the “loop gain” ► Label the summing node “B”…this is also known as the “feedback factor, β” ► In the plot window, plot V(AB)/V(B) …this is the open loop gain, Aol ► In the plot window, plot 1/V(B) …this is the ideal clo
Slide 43: Simulating for Stability
Simulating for Stability Aβ/β = Aol, the open loop gain Intercept occurs at 1.3 MHz, Same as ringing frequency in transient response 1/β = Acl, the ideal closed loop gain Rate of closure ~ 40dB/dec  unstable (or marginally stable) Analog Devices Confidential Information. ©2021 Analog Devices, Inc.
Slide 44: Simulating for Stability
Simulating for Stability Aβ 1/β Aol Aβ = 0 occurs at the same frequency as Aol = 1/β and provides the same information, the Rate of Closure method and Loop Gain method are just two ways of looking at the exact same thing Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights
Slide 45: Simulating for Stability
Simulating for Stability ► Using CF of 1 femtofarad (~0pF) We observe a rate of Closure of 40dB/dec indicating a stability issue ► Now, add a compensating capacitor CF to achieve ~45° of phase margin ► This is accomplished by placing the pole frequency right at the intercept of Aol and Acl (1/β) ► C
Slide 46: Simulating for Stability
Simulating for Stability 1 1 fZ = = 159kHz 100pF includes photodiode capacitance as 2π RF CIN 2π ×10k Ω ×100 pF well as input capacitance of the opamp fCOMP = f Z fU = 159kHz ×10 MHz =1.26 MHz 1 1 CF = = 12.6 pF  Use a standard value of 15pF for the 2π fCOMP RF 2π ×1.26 MHz ×10k Ω simulation (this
Slide 47: Simulating for Stability
Simulating for Stability It has been empirically determined that the demo hardware used later in this training has a combined PCB parasitic and self capacitance of RF of 1.5pF and will be included in the simulation Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserv
Slide 48: Simulating for Stability
Simulating for Stability Notice one or two visible bumps in the transient response, indicating 45° of phase margin Notice the pole frequency occurs at the intercept resulting in 45° of phase margin Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 4
Slide 50: Physically Connect PCB to ADALM2k
Physically Connect PCB to ADALM2k Top side of board has silk screen labelled ADALM2000 Carefully align pins and insert firmly ADALM2000 should be powered off when connecting or disconnecting the PCB Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024
Slide 52: Physically Connect the ADALM2k to the Laptop
Physically Connect the ADALM2k to the Laptop Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 52
Slide 55: The ADALM2k will Begin the Connection Process
The ADALM2k will Begin the Connection Process Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 55
Slide 58: Navigate to the Config File Location
Navigate to the Config File Location Load the file named “TIA Stability Scopy Time Domain Config.ini” Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 58
Slide 59: The O-Scope Will be Configured as Shown
The O-Scope Will be Configured as Shown Sets the time per division to 2µ/div Sets the Volts per division to 200mV/div Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 59
Slide 60: If You Click on the Power Supply Label
If You Click on the Power Supply Label You will see that indeed they are set to +/-5V and are reading back their measured voltages Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 60
Slide 61: Stability Demo PCB Schematic – No Jumper (J1) Installed
Stability Demo PCB Schematic – No Jumper (J1) Installed fCOMP = f Z fU f Z = zero frequency as a result of the photodiode capacitance reacting with the feedback resistor 1 fZ = 2π RF CIN fU = unity gain frequency of the amplifier 1 CF = 2π fCOMP RF Assume no jumpers are installed and no parasitic fe
Slide 62: Stability Demo PCB Schematic – No Jumper (J1) Installed
Stability Demo PCB Schematic – No Jumper (J1) Installed w/o parasitic AOL 1.5pF fCOMP 1/β w/ parasitic 1.5pF fZ fU Precision, Low-Noise, 10MHz Opamp: ADA4510 Input Bias Noise Spectral Unity Gain Input Capacitance Current Density Frequency Differential: 20 pF 10 pA (max) 5nV/√Hz 10.4 MHz Common-mode:
Slide 63: Stability Demo – No Jumper (J1) Installed
Stability Demo – No Jumper (J1) Installed Enable the Signal Generator and the Oscilloscope by clicking on the icon to the right o the instrument label You will see that indeed they are set to +/-5V and are reading back their measured voltages Analog Devices Confidential Information. ©2021 Analog Dev
Slide 64: Let’s Compensate for 45° of Phase Margin (CF = 15pF)
Let’s Compensate for 45° of Phase Margin (CF = 15pF) AOL fCOMP 1/β fZ fU fU ≈ 10MHz fZ ≈ 150 kHz CF ≈ 15pF fCOMP = 1.2 MHz Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 64
Slide 65: Place the Jumper (J1) for 45°
Place the Jumper (J1) for 45° Adjust the trigger level as needed Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 65
Slide 66: Let’s Overcompensate the Circuit, CF = 47pF
Let’s Overcompensate the Circuit, CF = 47pF AOL fCOMP 1/β fZ fU fU ≈ 10MHz fZ ≈ 150 kHz fCOMP ≈ 350 kHz CF = 47pF Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 66
Slide 69: Driving Capacitive Loads
Driving Capacitive Loads Seems stable, what could possibly go wrong? Let’s drive a 1nF load! Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 69
Slide 70: Driving Capacitive Loads
Driving Capacitive Loads Uh oh, looks much less stable. Why is this happening? Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 70
Slide 71: Driving Capacitive Loads
Driving Capacitive Loads ► The capacitive load is reacting with the output impedance of the amplifier and is adding a pole in the forward signal path ► Think of this as the Aol of the amplifier is “loaded” by the capacitive load IN- Zo CLoad IN+ About 100Ω at the unity gain frequency of 10 MHz AC An
Slide 72: Driving Capacitive Loads
Driving Capacitive Loads To determine the unity gain crossover Use the quadratic equation to find fu: frequency, we must solve this equation: 2 2 ( 1 2 2 2 ) ( f 4 + ( f p ) + ( f p ) f 2 + ( f p ) ( f p ) − ( AolDC ) ( f p ) ( f p ) = 1 2 2 2 1 2 0 2 ) −b ± b 2 − 4ac fu = 2a a =1 (( f ) + ( f ) ) =
Slide 73: Driving Capacitive Loads
Driving Capacitive Loads OK, now that we can visualized the issue, Open Loop Gain what is the solution? (dB) I` Datasheet Aol In the example using the ADA4510 and 1nF cap load: Second pole located at 1.6 MHz Loaded Aol UGF = 10 MHz 1/β Frequency Loaded fu =3.7 MHz (Hz) Analog Devices Confidential In
Slide 74: Driving Capacitive Loads
Driving Capacitive Loads Can I just add a zero into the transfer Open Loop Gain (dB) function? I` Datasheet Aol In the example using the ADA4510 and 1nF cap load: Second pole located at 1.6 MHz Loaded Aol UGF = 10 MHz 1/β So how do we fix it? Frequency (Hz) Add a zero and improve the Rate of Closure
Slide 75: Driving Capacitive Loads
Driving Capacitive Loads Aol 1 Zo -20dB/dec Fnewpole = 2π ( Z O + RS ) CLoad 2nd pole due to cap load reacting with Zo + RS Aol 1 Zero due to cap load Fpole = 2π Z O CLoad Zo reacting with RS 2nd pole due to cap RS load reacting with Zo -20dB/dec Aol CLoad 1 Zo Fzero = -40dB/dec 2π RS CLoad CLoad As
Slide 76: But Why Does RS Create a Zero in the Transfer Function?
But Why Does RS Create a Zero in the Transfer Function? Dominant pole Let’s start at DC…the Aol curve is Aol flat at the specified DC open loop Zo -20dB/dec gain RS As frequency increases, we first encounter the dominant pole CLoad Analog Devices Confidential Information. ©2021 Analog Devices, Inc.
Slide 77: But Why Does RS Create a Zero in the Transfer Function?
But Why Does RS Create a Zero in the Transfer Function? 2nd pole due to cap load reacting with Zo + RS Aol As frequency increases further, we encounter the pole due to the Zo -40dB/dec capacitive load reacting with the sum of Zo+Rs RS 1 CLoad Fnewpole = 2π ( Z O + RS ) CLoad Analog Devices Confident
Slide 78: But Why Does RS Create a Zero in the Transfer Function?
But Why Does RS Create a Zero in the Transfer Function? 2nd pole due to cap load reacting with Zo + RS Aol Zero due to cap load Further increasing frequency, the Zo reacting with RS capacitive reactance of CLoad RS -20dB/dec reduces to the value of Rs and introduces a zero CLoad 1 Fzero = 2π RS CLoa
Slide 79: But Why Does RS Create a Zero in the Transfer Function?
But Why Does RS Create a Zero in the Transfer Function? At frequencies beyond when the Aol capacitive reactance is less than Rs, the circuit starts to look like a Zo simple voltage divider RS Because we chose Rs ≈ |Zo|, the CLoad divider divides by two or thinking about it in dB terms, -6 dB Analog
Slide 80: But Why Does RS Create a Zero in the Transfer Function?
But Why Does RS Create a Zero in the Transfer Function? Once the load starts acting like a Aol simple voltage divider the impact Zo on the Aol curve is to simply offset RS the no cap load curve by -6 dB, i.e. -6 dB the rate of closure is -20 dB/dec Analog Devices Confidential Information. ©2021 Anal
Slide 81: Simulating Capacitive Loads – Step Cap Load, No RS
Simulating Capacitive Loads – Step Cap Load, No RS When you “break the loop” make sure that the capacitive load is still connected to the opamp output for proper simulation results Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 81
Slide 82: Simulating Capacitive Loads – Step Cap Load, No RS
Simulating Capacitive Loads – Step Cap Load, No RS Aol w/o cap load Aol w/ cap load Acl (1/β) Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 82
Slide 83: Simulating Capacitive Loads – Step RS, CLoad = 1nF
Simulating Capacitive Loads – Step RS, CLoad = 1nF Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 83
Slide 84: Simulating Capacitive Loads – Step RS, CLoad = 1nF
Simulating Capacitive Loads – Step RS, CLoad = 1nF Aol w/o RS Aol w/ RS Acl (1/β) Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 84
Slide 85: Simulating Capacitive Loads – Step Cap Load, RS = 100Ω
Simulating Capacitive Loads – Step Cap Load, RS = 100Ω Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 85
Slide 86: Simulating Capacitive Loads – Step Cap Load, RS = 100Ω
Simulating Capacitive Loads – Step Cap Load, RS = 100Ω Aol w/o CLoad Aol w/ CLoad Acl (1/β) 6dB Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 86
Slide 87: Demo Time - Navigate to the Config File Location
Demo Time - Navigate to the Config File Location Load the file named “Cap Load Stability Scopy Time Domain Config.ini” Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 87
Slide 88: The O-Scope Will be Configured as Shown
The O-Scope Will be Configured as Shown Sets the time per division to 1µs/div Sets the Volts per division to 100mV/div Analog Devices Confidential Information. ©2021 Analog Devices, Inc. All rights reserved. 30 May 2024 88
Slide 97: Quiz Answers
Quiz Answers Open Loop Gain ► What is DC Open Loop Gain in V/V? ► What is the slope from 10Hz to 1kHz? ► Phase shift at 100Hz? Ans: 10µV/V Ans: 0dB/dec Ans: ~0° ► What is GBP measured at a gain of 40dB? ► What is the slope from 1kHz to 1MHz? ► Phase shift at 1kHz? Ans: 8 MHz Ans: -20dB/dec Ans: 45°

Analog Devices — Technical Presentation (May 2024) on 6ix

Analog Devices — Technical Presentation (May 2024)

Slide 1: Stability Analysis of Voltage Feedback Opamps

Slide 2: Agenda

Slide 3: Acronyms Used In this Training

Slide 4: Acronyms Used In this Training

Slide 5: Bode Plot Review

Slide 6: Bode Plot Review

Slide 7: Let’s Add a Second Pole

Slide 8: Analysis by Inspection

Slide 9: Ideal 1st Order Open Loop Gain

Slide 10: Actual Open Loop Gain

Slide 11: Voltage Feedback Model

Slide 12: Ideal Closed Loop Gain

Slide 13: Stability Criteria

Slide 14: Rate of Closure

Slide 15: Quiz

Slide 16: Rate of Closure

Slide 17: 90° Phase Margin

Slide 18: 70° Phase Margin

Slide 19: 45° Phase Margin

Slide 20: 25° Phase Margin

Slide 21: Putting it All Together

Slide 22: Example Circuit 1: Analyze by Hand

Slide 23: Example Circuit 1: Analyze Using Simulation

Slide 24: Example Circuit 1: Transient Response

Slide 25: Example Circuit 2: Transimpedance Amplifier

Slide 26: Example Circuit 2: Transimpedance Amplifier

Slide 27: Example Circuit 2: Transimpedance Amplifier

Slide 28: Example Circuit 2: Transimpedance Amplifier

Slide 29: Example Circuit 2: Transimpedance Amplifier

Slide 30: Example Circuit 2: Transimpedance Amplifier

Slide 31: Example Circuit 2: Transimpedance Amplifier

Slide 32: Rule of Thumb - Increasing Cin

Slide 33: Rule of Thumb - Increasing Opamp BW

Slide 34: Rule of Thumb - Increasing RF

Slide 35: Rule of Thumb - Increasing Cf

Slide 36: Key Lessons Learned

Slide 37: Simulating for Stability

Slide 38: Simulating for Stability

Slide 39: Simulating for Stability

Slide 40: Simulating for Stability

Slide 41: Simulating for Stability

Slide 42: Simulating for Stability

Slide 43: Simulating for Stability

Slide 44: Simulating for Stability

Slide 45: Simulating for Stability

Slide 46: Simulating for Stability

Slide 47: Simulating for Stability

Slide 48: Simulating for Stability

Slide 49: Transimpedance Amplifier Hands On Demo

Slide 50: Physically Connect PCB to ADALM2k

Slide 51: Launch the Scopy Software

Slide 52: Physically Connect the ADALM2k to the Laptop

Slide 53: Click on the Icon

Slide 54: Click “Connect”

Slide 55: The ADALM2k will Begin the Connection Process

Slide 56: Successful Connection Looks Like This

Slide 57: Load the Config Files

Slide 58: Navigate to the Config File Location

Slide 59: The O-Scope Will be Configured as Shown

Slide 60: If You Click on the Power Supply Label

Slide 61: Stability Demo PCB Schematic – No Jumper (J1) Installed

Slide 62: Stability Demo PCB Schematic – No Jumper (J1) Installed

Slide 63: Stability Demo – No Jumper (J1) Installed

Slide 64: Let’s Compensate for 45° of Phase Margin (CF = 15pF)

Slide 65: Place the Jumper (J1) for 45°

Slide 66: Let’s Overcompensate the Circuit, CF = 47pF

Slide 67: Place the Jumper (j1) for >70°

Slide 68: Driving Capacitive Loads

Slide 69: Driving Capacitive Loads

Slide 70: Driving Capacitive Loads

Slide 71: Driving Capacitive Loads

Slide 72: Driving Capacitive Loads

Slide 73: Driving Capacitive Loads

Slide 74: Driving Capacitive Loads

Slide 75: Driving Capacitive Loads

Slide 76: But Why Does RS Create a Zero in the Transfer Function?

Slide 77: But Why Does RS Create a Zero in the Transfer Function?

Slide 78: But Why Does RS Create a Zero in the Transfer Function?

Slide 79: But Why Does RS Create a Zero in the Transfer Function?