Slide 1: Introducing ST Neural-ART Accelerator
Introducing ST Neural-ART Accelerator Enabling high-end, power-efficient edge AI performance on MCUs. ST Restricted
Slide 2: Redefining product greatness
Redefining product greatness AI AI drives smarter products and new business models ST Restricted
Slide 3: Cloud processing for AI & IoT: Generating a tsunami of data
Cloud processing for AI & IoT: Generating a tsunami of data Cloud based AI (IoT devices) AI AI inference & storage 120 ZetaBytes data generated in 2024 > 180 ZetaBytes in 2025 Source: explodingtopics.com ST Restricted
Slide 4: The rise of edge AI: AI at device level
The rise of edge AI: AI at device level Edge AI (distributed AI) (AI) Optional distributed cloud AI AI & storage ST Restricted
Slide 5: Edge AI acceleration requires new architectural solution: the NPU
Edge AI acceleration requires new architectural solution: the NPU 160 140 120 IMAGES / WATT 100 80 60 40 20 0 CPU FPGA GPU NPU GPU: graphic accelerator NPU: neural processing unit (AI accelerator) Source W. Dally ST Restricted
Slide 6: From DMIPS to TOPS, the paradigm shift
From DMIPS to TOPS, the paradigm shift Opening a new range of embedded AI applications Object segmentation Microcontrollers localization (Arm® Cortex® -M) Microcontrollers with NPU accelerator Pose estimation Mono-modality workloads Multi-modality workloads Object classification Speech Static single
Slide 7: Neural-ART Accelerator architecture overview
Neural-ART Accelerator architecture overview Neural-ART Accelerator • A paradigm shift from the Von Neumann Reconfigurable architecture towards a flexible, dedicated dataflow CNN* inference engine stream processing engine. NPU Logic • Hardware acceleration for a wide range of neural network architec
Slide 8: Neural-ART Accelerator in STM32N6 MCU
Neural-ART Accelerator in STM32N6 MCU Dedicated embedded neural processing unit • 600 GOPS • 3 TOPS/W power consumption • Cache memory to optimize external memory access ML performance uplift* Dataflow stream processing engine reduces MCU memory throughput requirements and power consumption Neural S
Slide 9: Neural-ART Accelerator provides a huge performance leap for AI inference
Neural-ART Accelerator provides a huge performance leap for AI inference Inference per second 120 x26 100 80 x116 60 x66 x127 x59 40 • MobileNet v1: image classification • MobileNet v2: image classification 20 • TinyYolo v2: object detection • Yolov 8n : object detection 0 • Yamnet 1024: audio recog
Slide 10: Seamless integration with existing software ecosystem
Seamless integration with existing software ecosystem Generate optimized ST Edge AI model zoo Optimize and benchmark your NN model code and project files OR Bring Your Own Model Graph optimizer Quantizer Memory optimizer STM32 Neural-ART Accelerator Online platform / Rest API / Desktop tool / CLI ST
Slide 11: Reach the full potential of your application
Reach the full potential of your application 50+ case studies 10+ free software tools Unified ST Edge AI core technology ST Restricted
Slide 12: Neural-ART Accelerator outlook
Neural-ART Accelerator outlook 2x Analog / Digital NPU with Energy efficiency in-memory computing 6x Computational Processing memory unit (NPU) Conventional Processing memory unit Digital (NPU) in-memory computing Von Neumann evolution + hardware acceleration Computing power ST Restricted
Slide 13: More about next generations Neural-ART Accelerator
More about next generations Neural-ART Accelerator Neural-ART Accelerator • In-memory cell arithmetic significantly reduces Convolutions are processed data transfer with memory hence power directly within the memory consumption. DIMC RAM • Achieves up to 6x improvement in TOPS and Conv Conv Conv TOP
Slide 14: Read the whitepaper to know more
Read the whitepaper to know more © STMicroelectronics - All rights reserved. ST logo is a trademark or a registered trademark of STMicroelectronics International NV or its affiliates in the EU and/or other countries. www.st.com/trademarks For additional information about ST trademarks, please refer