Slide 1: Investor Presentation
Investor Presentation March 2024 Atomera Incorporated 1
Slide 2: Safe Harbor
Safe Harbor This presentation contains forward-looking statements concerning Atomera Incorporated (““Atomera,” the “Company,” “we,” “us,” and “our”). The words “believe,” “may,” “will,” “potentially,” “estimate,” “continue,” “anticipate,” “intend,” “could,” “would,” “project,” “plan,” “expect” and s
Slide 3: Investment Overview
Investment Overview ► Mears Silicon Technology (MST ®) is a thin film used to enhance semiconductors ▪ Results in higher performance, lower power, and lower costs for ICs ► Capital-light IP and technology licensing business ► Engaged with 50% of world’s top semiconductor makers ► Licenses with five
Slide 4: MST Technology
MST Technology Potential Benefits ► Improved Efficiency ▪ Higher transistor performance ▪ Lower power consumption ▪ Better reliability ► Lower cost ▪ Reduced die size ▪ Improved yield ▪ Higher throughput ► Same benefits as a node shrink Atomera Incorporated 4
Slide 5: Target Customers & Partners
Target Customers & Partners Integrated Device Manufacturers Foundry Fabless Tool Suppliers (Partners) Atomera Incorporated 5
Slide 6: Customer Pipeline
Customer Pipeline v Customer Wafer Manufacturing Atomera MST® Deposition Customer MST® Deposition Phase 1. Planning 2. Setup 3. Integration 4. Installation 5. Qualification 6. Production Number of Customer Engagements 27 24 21 18 15 12 9 6 3 0 2016 2017 2018 2019 2020 2021 2022 2023 Phase 1 Phase 2
Slide 7: Customer Engagement & Revenue Model
Customer Engagement & Revenue Model v Customer Wafer Manufacturing Atomera MST® Deposition Customer MST® Deposition 1. Planning 2. Setup 3. Integration 4. Installation 5. Qualification 6. Production Phase Engineering Service • MST deposition on customer wafers Fees • Integration consulting • Integra
Slide 8: Atomera Incorporated
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Slide 9: ST Path to Production
ST Path to Production Customer Wafer Manufacturing Atomera MST ® Deposition Customer MST® Deposition 1. Planning 2. Setup 3. Integration 4. Installation & Productization 5.Qualification 6. Production Phase Integration Manufacturing Distribution License License License Royalties Fee Fee Fee Complete
Slide 10: Productization cycle
Productization cycle Phase 5 Phase 6 Process development with TCAD Freeze PDK Process Volume (Process Design Kit) Production Wafers Qualification MST Silicon manufactured Installation Validation with MST Phase 4 Chip ChipDesigns Designs Chip Designs Start Chip Designs Start Start Atomera Incorporate
Slide 11: MST Key Benefits Across Nodes
MST Key Benefits Across Nodes Leading Analog & Mainstream FinFET GAA RF SOI Planar Mobility 8% 20% 25% 10% 15+% Dopant Engineering 20% 15% 15% 15% 20% Reliability (TDDB/BTI) 25% 25% 25% 25% 180nm 130nm 90nm 65nm 40nm 28nm 22nm 16/14nm 10nm 7nm 5nm 2nm These Benefits are ADDITIVE & COMPLEMENTARY to o
Slide 12: MST technology focus areas
MST-SP, MST SPX technology focus areas MST for RF-SOI MST for Advanced Nodes MST for DRAM Atomera 12
Slide 13: MST optimizes AI performance
MST optimizes AI performance ► AI algorithms are driving unparalled computing demands ▪ Exceeding ideal single chip silicon area which impacts yield ► Heterogenous chiplet architectures solve this problem ► Small chiplet designs can be optimized by process node ► MST’s ability to enhance mature node
Slide 14: MST-SPX targeting power devices
MST-SPX targeting power devices ► Targets higher voltage (5-40V) product area Rsp vs. BVdss ► Strong customer demand for solutions Si control Rsp vs. BV Plot ► MST brings significant improvement Si control ▪ Early results showing gains in many areas 38% MST Better -38% ▪ Allows manufacturers to shri
Slide 15: MST: Solving GAA Transistor Challenges
MST: Solving GAA Transistor Challenges ► Blocks source/drain dopant diffusion ► Lowers contact resistance ► Provides enhanced punch-through stop ► Reduces HKMG stack height layer between source and drain ► Improves carrier mobility, gate leakage Transistor Architectural Evolution Atomera Incorporate
Slide 16: Variability reduction with MST
Variability reduction with MST ► High variability between transistors is a significant issue ▪ A big driver of variability is Random Dopant Fluctuation (RDF) Vt difference in a matched transistor pair ▪ Some transistors are designed larger to account for variability ▪ This increases costs and limits
Slide 17: Royalty Opportunity
Royalty Opportunity ► ~410 wafer fabs operating worldwide ► Adoption of MST in one fab can make Atomera profitable from royalties alone ▪ 2023 non-GAAP OPEX guidance is $16.25M - $16.75M Example 1 | Worldwide Average Fab Example 2 | Leading Foundry, 28nm Fab Monthly Fab Capacity 1 Monthly Fab Capaci
Slide 18: MST Customer Business Opportunity
MST Customer Business Opportunity ► Foundry economics Wafer GM$ MST Wafer Price GM% Increase Royalty Cost 28nm HP wafer $ 3,300 45% $ - $ - $ 1,815 28nm HP+ wafer $ 3,450 45% $ 68 $ - 5% higher price for +15% performance boost 28nm HP wafer with MST $ 3,600 47.0% $ 208 $ 72 $ 1,907 30% performance b
Slide 19: Financial Review
Financial Review Income Statement Three Months Ended ($ in thousands, except per-share data) 3/31/23 6/30/23 9/30/23 12/31/23 FY 2023 REVENUE $ - $ - $ - $ 550 $ 550 Gross Profit - - - 522 522 OPERATING EXPENSES Research & Development 3,036 3,192 3,305 2,992 12,525 General and Administration 1,742 1
Slide 20: Summary
Summary ► High margin, recurring revenue financial model ► Strong technology, patent position, and balance sheet ► Traction with many top industry players and growing licensee base ► Ramping commercial license revenues Atomera Incorporated 20
Slide 21: Thank You
Thank You Atomera Incorporated 21
Slide 22: Backup Slides
Backup Slides Atomera Incorporated 22
Slide 23: Customer Engagement Model
Customer Engagement Model Customer Wafer Manufacturing Standard customer engagement Atomera MST® Deposition Customer MST ® Deposition Planning Setup Integration Installation Qualification Production Phase Joint development 1 Atomera MST® Deposition Customer MST ® Deposition JDA Completion Planning S
Slide 24: MST-SP
MST-SP ► MST-SP is a highly-engineered asymmetric power device ▪ Uses MST to enhance Idlin and precisely control dopant profiles ► Improves 5V power devices G ▪ Lower RSP B S D ▪ Can be traded for up to 20% smaller area ► Targeted for rapidly-growing PMIC market 24
Slide 25: 5V Transistors – Critical and Growing Market
5V Transistors – Critical and Growing Market ► Targeted at rapidly-growing PMIC (Power Management IC) market ▪ Power devices can be up to 80% of PMIC die area ► All ICs need stable, regulated power ▪ Across battery charge level, lifetime degradation, and load ▪ Across usage modes – DVS (Dynamic Volt
Slide 26: Example: Use Of 5V Transistor In Apple iPhone13
Example: Use Of 5V Transistor In Apple iPhone13 13 of 25 IC’s in Apple iPhone13 Pro use 5V transistors ▪ iPhone 13 Pro teardown by Tech Insigths ▪ 5V transistor assessment by Atomera Reference https://www.techinsights.com/blog/teardown/apple-iphone-13-pro-teardown?utm_source=Prospect+Email&utm_mediu
Slide 27: 5V MST-SP Product – Value Proposition
5V MST-SP Product – Value Proposition ► Industry best performance at 180nm (Rsp) ▪ Based on measured silicon data ▪ Scalable to smaller process nodes Gate G B S D ► Meets all reliability requirements Source Drain ▪ Breakdown Voltage (BVDSS) > 10.5V MST MST ► Significant cost savings, performance ben
Slide 28: Atomera MSTcad
Atomera MSTcad ► Leading semiconductor companies use TCAD to model manufacturing processes ▪ MSTcad is an add-on for MST ► MSTcad can speeds up the time needed to evaluate multiple MST integration options ► Lowers cost of MST evaluation ► Speeds time to successful wafer runs ► Fewer wafer runs lead
Slide 29: MST enables legacy capacity expansion
MST enables legacy capacity expansion ► MST provides 30% performance advantage ▪ 0.13u analog design ▪ MST vs control silicon ► Enables a die shrink of 15-20% ► Smaller die means more manufacturing capacity ▪ Without the cost of building a new fab Atomera Incorporated 29
Slide 30: MST 28nm benefits
MST 28nm benefits MST shows 30% ► Performance improvements due to MST can be higher performance traded for area reduction ► 28nm PDK SPICE model used to showcase: ▪ Logic scaling with MST shows 22-25% area reduction • Using a NAND2 gate ▪ Analog scaling with MST shows up to 21% area reduction ► Impl
Slide 31: MST for High-k metal gate (HKMG) transistors
MST for High-k metal gate (HKMG) transistors ► MST enhances HKMG transistor performance and reliability* ▪ Reduced stress induced leakage current (SILC) enabling reliability improvement ▪ 23% long-channel mobility enhancement ▪ 2.7x lower gate leakage SILC e- mobility JG vs. EOT * Professor Suman Da
Slide 32: MST: Mears Silicon Technology
MST: Mears Silicon Technology Quantum Engineered Silicon Partial Monolayers of MST Enhanced Oxygen in Silicon Transistors Supported by Major Semiconductor Tool Suppliers Atomera Incorporated 32
Slide 33: Atomera state of the art research center
Atomera state of the art research center ► Epi deposition facility ▪ 300mm Epi deposition ▪ 200mm Epi deposition ▪ Wafer cleaning equipment ▪ Metrology tools ▪ Advanced wafer handling ▪ World class clean room facility ► Available to deliver customer wafers Epi Deposition Tool Atomera Incorporated 33
Slide 34: Atomera MSTcad Progress
Atomera MSTcad Progress ► Leading semiconductor companies use TCAD ► MST is modelled with a TCAD add-on called MSTcad ► These plots show silicon verification of MSTcad simulations ► Enables good electrical match-up for 5V NMOS and MST SP ► Should speed time to successful results with customers Atome
Slide 35: MST1 vs MST2
MST1 vs MST2 ► MST1 ▪ Blanket technology ▪ Easy to integrate ▪ Deposited at beginning of mfg process ▪ Degraded by high heat in STI/Well module ▪ Faster time to market for low heat processes ▪ Used for FinFET, RFSOI, newer process nodes ► MST2 ▪ Selective technology • Integrated after STI/Well so av