Verisilicon Microelectronics (shanghai) Co., Ltd. Class A · SSE:688521
Verisilicon Microelectronics (shanghai) Co., Ltd. Class A — VeriSilicon — Technical Presentation (November 2002)
34 slides from Verisilicon Microelectronics (shanghai) Co., Ltd. Class A's technical presentation, November 2002
Slide 1: Algorithmic & Implementation Aspects of Echo Cancellation in Packet Voice Networks
ALGORITHMIC & IMPLEMENTATION ASPECTS OF ECHO CANCELLATION IN PACKET VOICE NETWORKS Krishna V V, Jitendra Rayala, Brendon Slade LSI Logic, Milpitas, CA 36th Asilomar Conference on Signal, Systems and Computers, November 2002
Slide 2: Overview
Overview • Echo cancellation (EC) in telephony • EC in packet voice networks – Customer premise equipment (CPE) – Packet voice gateways (PVG) • Current PVG channel capacities • Role for DSPs in packet voice networks • Design / algorithmic / implementation Issues • Issues & possibilities for near fut
Slide 3: Echo Sources in Telephony
Echo Sources in Telephony Echo arises due to impedance mismatches at hybrids. Central Central Office, A Office, B Rx-A 2-wire 2-wire Rx-B local loop local loop 4-wire AH2 AH1 segment BH2 BH1 Tx-A Tx-B Near Echo for A: Far Echo for A: Leakage at AH1 Leakage at BH2 + Reflection at AH2. + Reflection at
Slide 4: Echo Canceller Evolution
Echo Canceller Evolution Bigger delays. More channels. Even more channels. Better quality. Longer Tails. Lower costs. Long Recent More Near Ago past recently future ~ (1920 – 1990) ~ (1982 – 1995) ~ 1995 – 2002 2003 – 2006 Echo suppressors Short tail line Multiple strains Denser, (loss switches) ech
Slide 5: EC: The Past Decade
EC: The Past Decade Early 90’s Late 90’s Early 00’s EC channels per board ~ (12 - 24) ~ (24 - 256) ~ (64 – 672+) Power per channel* ~ 120 mW ~ 10 - 25 mW ~ 5 - 15 mW Cost per channel* ~ $20 - 25 ~ $4 - 5 ~ $2 Major Long distance Long distance Cellular networks; markets POTS networks POTS networks; P
Slide 6: EC for Packet Voice
EC for Packet Voice Central Office EC EC EC EC EC IP CPE Cloud Gateway PSTN Quiz: Cloud 2-wire link Why EC in the Gateway? “4-wire” link Digital phones, without hybrids? Nov 3, 2002 Asilomar SS&C 2002 / LSI Logic 6
Slide 7: EC in PVG: Key Requirements
EC in PVG: Key Requirements • Cost / channel – DSP solutions à MHz; Memory; Device choice – Custom processors à Die size; Technology choice • Power consumption / channel – Lower the better Nov 3, 2002 Asilomar SS&C 2002 / LSI Logic 7
Slide 8: Acoustic / Line Echo
Acoustic / Line Echo ITU Standard: G.167-1996 G.168-2002 Tail Capacity: 64 – 128 ms (typ.); 16 – 64 ms (typ.); As long as 250 ms As long as 128 ms Sampling Rate: 8 kHz, 16 kHz 8 kHz Echo path Dispersive, but decays Sparse (typ. dispersion Characteristics : with time. lengths < 10ms). Rapidly time va
Slide 9: Role For DSPs
Role For DSPs • Increased clock speeds (typical > 10-20X) – 15MHz to 300MHz++ • Higher performance / clock tick (typical 2-4X) – Parallelism – VLIW, Super-scalar with multiple resources – LMS specific instructions – Optional HW / coprocessor support – Multi-core standard products (dual or quad core)
Slide 10: EC – A Black-box View
EC – A Black-box View ROUT (to near-end) RIN Echo (LRIN) (LECHO) G.168 EC SIN SOUT Near-end (LRES or LRET) signal Control Status Nov 3, 2002 Asilomar SS&C 2002 / LSI Logic 10
Slide 11: EC: Ground Truths
EC: Ground Truths • Line echo cancellers are more than just adaptive filters. – Adaptation control, non-linear processor, comfort noise injection, V.25 tone detection, etc. are non-trivial in terms of design and /or resource requirements. • The G.168 specification does not specify any one design or
Slide 12: Key Performance Issues
Key Performance Issues • Fast initial convergence • Low steady-state residual • Robust convergence with noisy near-end (SIN) • Fast tracking (for occasional path changes) • NLP and CNI support • High voice quality (for near-end speech) Nov 3, 2002 Asilomar SS&C 2002 / LSI Logic 12
Slide 13: G.168 EC Internals
G.168 EC Internals Rout Rin Enable V.25 Tone EC Detector; Control Logic Disable (Adaptation, Holding-band NLP) Logic Nonlinear Sin Processor (NLP); Comfort Noise (CNI) Sout Nov 3, 2002 Asilomar SS&C 2002 / LSI Logic 13
Slide 14: A Grip on EC Complexity
A Grip on EC Complexity NLMS based Example: Data Ops / Sample Memory FIR O(N) O(N) For lattice structures, Filtering: filtering and update Filter stage break-up not O(N)-O(2N) O(N) possible. Updates: Costs are almost constant Other ~ ∆c ~ ∆M (depends very weakly on Logic*: filter length, N). * Other
Slide 15: Processor Loading
Processor Loading MACs / cycle: 1 2 4 FIR O(N) O(N/2) O(N/4) Filtering: Filter O(N/4) - Updates: O(N)-O(2N) O(N/2)-O(N) O(N/2) Other Logic: ~ ∆c ~ ∆c ~ ∆c Percentage load Load for ~ 12 – 13 ~8–9 ~5–6 for “other logic” 64ms EC (MHz) (MHz) (MHz) is significant. Nov 3, 2002 Asilomar SS&C 2002 / LSI Log
Slide 16: Cost Summary
Cost Summary • Two key factors in overall cost: – Processing load – Data memory • Both of these costs depend critically on – EC design – Adaptation technique – Processing platform (DSP, ASIC, …) – Implementation efficiencies Nov 3, 2002 Asilomar SS&C 2002 / LSI Logic 16
Slide 17: EC Cost Survey
EC Cost Survey Commercial 32ms tail G.168 solutions (July 2002) 2800 Data 2200 Memory (bytes / channel) 1600 1000 3 4 5 6 7 8 9 10 11 DSP MHz à Nov 3, 2002 Asilomar SS&C 2002 / LSI Logic 17
Slide 18: A Few EC Design Options
A Few EC Design Options “Tail independent” / “Full tail” “Floating window” Single filter with Double filter with robust control simpler controls Time Transform Subband domain domain structure Nov 3, 2002 Asilomar SS&C 2002 / LSI Logic 18
Slide 19: Full Tail / Floating Window
Full Tail / Floating Window 128 ms Actual echo path Full tail solution 2-window solution 12 ms 12 ms Nov 3, 2002 Asilomar SS&C 2002 / LSI Logic 19
Slide 20: Full Tail / Floating Window
Full Tail / Floating Window FULL TAIL FLOATING WINDOW • Requires more processing for • Useful for long tails, where the both filtering and updates extra cost of window finding • Convergence speed is logic can be absorbed. reduced (for NLMS methods) • Improved performance with • Full tail EC is also
Slide 21: Full / Floating Window EC
Full / Floating Window EC 16 Both versions include Full Tail EC V.25 tone disabler, and 12 comply with G.168 MHz Window EC requirements. 8 Blue markers indicate actual MHz loading on 4 a 16-bit DSP. Yellow markers are estimates. 8 16 32 64 96 128 Echo Tail Support (ms) à Nov 3, 2002 Asilomar SS&C 20
Slide 22: Double Filter Design
Double Filter Design ROUT RIN Simplifies adaptation control; improved double-talk resistance. Adaptive Fixed Extra processing and Filter Copy Filter data memory needed. (under control) The additional load SIN can be reduced if the SOUT fixed filter makes use of windowing. Nov 3, 2002 Asilomar SS&C 2
Slide 23: Adaptation Options
Adaptation Options • NLMS (sample rate or block adaptive) • Enhanced NLMS variants (decorrelation, variable step size, PNLMS, PNLMS++) • Fast affine projection (FAP) • Fast RLS (FTRLS, QR-RLS, …) • Other methods also exist … Nov 3, 2002 Asilomar SS&C 2002 / LSI Logic 23
Slide 24: Costs of Adaptation
Costs of Adaptation MACs / Sample* Data Memory / Channel NLMS O(2.N) ~ O(2.N) APA (order P) O(2.PN) + O(7.P2) ~ O(2.PN) FAP (order P) O(2.N) + O(20.P) ~ O(2.N) PNLMS O(4.N)* ~ O(2.N) FTRLS O(8.N)* ~ O(7.N) * MACs/sample is not a good measure for PNLMS and FTRLS. Nov 3, 2002 Asilomar SS&C 2002 / LSI
Slide 25: Simulations
Simulations • Composite source signal (CSS) used. • Echo paths from G.168-2002 specification. • 16-bit quantization applied to input / output signals and the filter coefficients. • Convergence measured for noise-free inputs. • Adaptation step-size selected to meet performance requirements for noisy
Slide 26: NLMS: Initial Convergence
NLMS: Initial Convergence ACOM (dB) for NLMS, 128ms (full tail), µ=0.2: Time (in sec) → Echo path 0.5 0.75 1.0 2.0 3.0 4.0 #5 20.2 22.1 24.3 28.2 30.2 31.1 #6 16.0 16.9 18.3 21.6 24.0 25.8 #7 17.6 18.2 19.2 21.7 23.6 25.3 Nov 3, 2002 Asilomar SS&C 2002 / LSI Logic 26
Slide 27: Towards “steady-state”
Towards “steady-state” ACOM (dB) for NLMS, 128ms (full tail), µ=0.2: Time (in sec) → Echo path 0.5 1.0 2.0 4.0 8.0 10 15 #5 20.2 24.3 28.2 31.1 29.6 28.9 28.0 #6 16.0 18.3 21.6 25.8 28.3 29.8 28.6 #7 17.6 19.2 21.7 25.3 27.6 29.3 27.6 Nov 3, 2002 Asilomar SS&C 2002 / LSI Logic 27
Slide 28: Pre-whitening Remedy
Pre-whitening Remedy Echo Path #7; 128ms full tail, µ=0.2 for all methods Time (in sec) → Method 0.5 1.0 2.0 4.0 8.0 10 15 NLMS: 17.6 19.2 21.7 25.3 27.6 29.3 27.6 NLMS-pw 22.2 27.4 33.8 35.9 35.3 34.5 34.0 ? ? Nov 3, 2002 Asilomar SS&C 2002 / LSI Logic 28
Slide 29: More “Cheap” Options
More “Cheap” Options Echo Path #7; 128ms tail; µ=0.2 for all methods Time (in sec) → Method 0.5 1.0 2.0 4.0 8.0 10 15 NLMS: 17.6 19.2 21.7 25.3 27.6 29.3 27.6 NLMS-pw 22.2 27.4 33.8 35.9 35.3 34.5 34.0 PNLMS 25.0 27.0 30.1 33.8 34.6 34.6 33.0 APA-2 25.6 32.4 39.1 39.7 37.6 37.6 36.4 Nov 3, 2002 Asil
Slide 30: Brawn vs. Brain?
Brawn vs. Brain? Echo Path #7; 128 ms tail; µ=0.2 for all methods Time (in sec) → Method 0.5 1.0 2.0 4.0 8.0 10 15 NLMS: 17.6 19.2 21.7 25.3 27.6 29.3 27.6 NLMS-pw 22.2 27.4 33.8 35.9 35.3 34.5 34.0 PNLMS 25.0 27.0 30.1 33.8 34.6 34.6 33.0 APA-2 25.6 32.4 39.1 39.7 37.6 37.6 36.4 16ms Window 47.0 50
Slide 31: Multi-channel EC Costs
Multi-channel EC Costs • Processor load (MHz or gates): – Increases almost linearly with channel count – Some (significant) savings can be exploited • Data Memory (Channel object): – Increases linearly with channel count Nov 3, 2002 Asilomar SS&C 2002 / LSI Logic 31
Slide 32: Trimming Multi-channel Costs
Trimming Multi-channel Costs • Budget reduction using telephone call characteristics – Easier to tap, when one EC resource handles a large number of calls (more the merrier); no explicit control needed • Apply adaptation only on “as needed” basis – Abrupt changes in echo tail are rare. Subsequent to
Slide 33: Example: 84-channel EC Device
Example: 84-channel EC Device Ball-park Numbers: Processor Clock: 400 – 650 MHz Data Memory: ~ 4 Mbits Data I/O 520 – 600 Mb/s Bandwidth: Assumptions: 128 ms tail echo cancellation. 4.5 – 7.5 MHz per channel. 5200 – 5600 Bytes of data memory per channel ( ~ O(2N) with 16-bits / word). Higher density
Slide 34: Summary
Summary • Packet voice gateways require 1000’s of long tail (~64-128 ms) echo cancellers • Power and cost efficient solutions require prudent selection from available design / implementation choices, based on both processing as well as data memory complexities. • “Tail-independent” designs offer bot