Slide 1: TWS Solution Using Andes D25+ACE
TWS Solution Using Andes D25+ACE Wei Tung 2020/04/23
Slide 2: Highlights of TWS with ACE
Highlights of TWS with ACE Function Name Insn cycles ACE cycles Speedup FIR (128 taps) 1692 128 12x LMS (128 taps) 1820 128 14x Data transfer bus traffic background ANC Hybrid Solution 10404 250 40x - Noise Control Driving Innovations™
Slide 3: Agenda
Agenda TWS Platform Andes V5 Role in TWS D25 + ACE TWS Solution TWS ACE Instruction Driving Innovations™ 1
Slide 4: TWS Platform Introduction
TWS Platform Introduction Driving Innovations™ 2
Slide 5: TrueWireless Stereo (TWS) Platform
TrueWireless Stereo (TWS) Platform Playback sync: TrueWireless™ Stereo Bluetooth Version: Bluetooth 5.0, 4.2 Bluetooth Technology: Dual-mode, Single, BLE ANC: Feedforward, Feedback, Hybrid Audio interface: I2S, SPDIF, DAC MIC: N * AMIC, N * DMIC Driving Innovations™ 3
Slide 6: TWS Challenges
TWS Challenges Audio playback synchronization • PLL accuracy • Playback start timing Active noise control computation ACE • High amount of computation • Low latency data path requirement Audio codec and audio format conversion • PCM(24bits), little endian, big endian ACE • LDAC, APTX, AAC Co
Slide 7: TWS Platform
TWS Platform CPU RF Baseband Controller (with DSP insn) BT memory DSP PLL PLL PLL CPU AUD BT AXI/AHB Hardware DMA ADC Audio subsystem Bus Matrix GPIO DAC I2C APB Bridge PWM/PIT RTC Internal memory SPI UART WDT Driving Innovations™ 5
Slide 8: ANC Challenges in TWS
ANC Challenges in TWS ANC challenges • Restrict latency • Real time sample base streaming (1 sample in, 1 sample out) • Limited resource with high computation requirement • Low power, Low latency, High sample rate ADC & DAC Example: 1 • ADC & DAC in 192KHz (1 sample = ~= 5us) 192𝐾𝐻𝑧 • CPU…
Slide 9: ANC Algorithm (Hybrid)
ANC Algorithm (Hybrid) • For higher noise control performance, the higher filter tap number should be used • For example: how many addition and multiplication are needed for 128 taps ? • Total 896 additions & 896 multiplications for9 1 sample Driving Innovations™ 7
Slide 10: ANC Conclusion
ANC Conclusion Example: 1 • ADC & DAC in 192KHz (1 sample = 192𝐾𝐻𝑧 ~= 5us) • CPU clock 160MHz • The algorithm should be finished in 800 clock cycles. (160M * 5us = 800) • ANC Feedforward : Total 384 MACs for 1 sample • ANC Hybrid : Total 896 MACs for 1 sample Driving Innovations™ 8
Slide 11: ANC FIR & LMS Profiling
ANC FIR & LMS Profiling Single 128-tap FIR takes about 1600 cycles Single 128-tap LMS takes about 1800 cycles Driving Innovations™ 9
Slide 12: ANC in Hardware
ANC in Hardware Advantage Disadvantage 1. Parallel computing 1. Fixed architecture, Fixed algorithm 2. Optimized data path 2. Complicated SRAM access Absolute Efficiency (not flexible) Complete Flexibility (power consuming) Mul Add Add Mul ANC hardware Add Mul Mul Mul Add Add Mul Add Add Add Add Mul
Slide 13: Andes V5 Role in TWS
Andes V5 Role in TWS Driving Innovations™ 11
Slide 14: Andes V5 Role in TWS
Andes V5 Role in TWS • CPU + DSP ▪ Lots of redundant functions • DSP + DSP ▪ Lots of redundant functions • D25 + ACE ▪ Best choice for TWS! Driving Innovations™ 12
Slide 15: TWS Platform
TWS Platform RF Baseband Controller D25F (RISC-V with CPU + PDSP extension) Exchange memory ACE ( backgroud fir) (64KB) ACE (e.g background lms) ACE (e.g background dma) PLL PLL PLL CPU AUD BT AXI/AHB ADC Audio subsystem Bus Matrix APB Device APB Bridge DAC Internal memory (192KB, 256KB, 384KB) Driv
Slide 16: D25 + ACE TWS Solution
D25 + ACE TWS Solution Driving Innovations™ 14
Slide 17: ANC: D25 W/ ACE Solution
ANC: D25 W/ ACE Solution 1 Sample 1 Sample 1 Sample 1 Sample 1 Sample 1 Sample 800 cycles 800 cycles 800 cycles 800 cycles 800 cycles 800 cycles Audio codec MISC routine Audio codec MISC routine Audio codec MISC routine Software solution DMA BT control flow DMA 128 taps FIR flow BT control DMA 128BT
Slide 18: ANC: D25 W/ ACE Solution
ANC: D25 W/ ACE Solution ANC control Audio codec MISC routine ANC Hybrid solution (low power, small area) DMA BT control flow 800 cycles Bg DMA time Bg 128 taps FIR (Shat) Bg 128 taps FIR (Shat) Bg 128 taps FIR (Shat) Bg 128 taps LMS Bg 128 taps LMS Bg 128 taps FIR (ADAP) Bg 128 taps FIR (ADAP) Driv
Slide 19: ANC: D25 W/ ACE Solution
ANC: D25 W/ ACE Solution Example: 1 • ADC & DAC in 192KHz (1 sample = 192𝐾𝐻𝑧 ~= 5us) • CPU clock 160MHz • The algorithm should be finished in 800 clock cycles. (160M * 5us = 800) Example (with ACE): 1 • ADC & DAC in 192KHz (1 sample = 192𝐾𝐻𝑧 ~= 5us) • CPU clock 80MHz • The algorithm…
Slide 20: TWS D25+ACE Solution
TWS D25+ACE Solution ram coef_sram { //coef. Custom Memory //ACE_BEGIN: fir_cal } reg [31:0] fir_out_reg; wire [31:0] acc; ram data_sram{ //vector Custom Memory } assign acc = (ace_vstart) ? 64'd0 : fir_out_reg; vec bg_insn fir_cal { assign fir_out = coef32[31:0] * buf32[31:0] + acc; operand=…; alwa
Slide 21: TWS ACE Instruction Introduction
TWS ACE Instruction Introduction Driving Innovations™ 19
Slide 22: 128-Tap FIR Instruction
128-Tap FIR Instruction 𝑀 for (int k = 0; k < M; k++) 𝑊 𝑧 ⇒𝑦 𝑛 = 𝑊𝑘 ∗ 𝑥[𝑛 − 𝑘] Y += (W[k] * X[k]); //calculate filter output 𝑘=0 ACM (data buf) D Q ACR Ready for audio out ACE tool generated ACM (coef) Define by user Driving Innovations™ 20
Slide 23: D25 ACE Platform
D25 ACE Platform lms_cal0 fir_cal0 lms_cal1 fir_cal1 fir_cal2 bt_dma Driving Innovations™ 21
Slide 24: Highlights of TWS with ACE
Highlights of TWS with ACE Function Name Insn cycles ACE cycles Speedup FIR (128 taps) 1692 128 12x LMS (128 taps) 1820 128 14x Data transfer bus traffic background ANC Hybrid Solution 10404 250 40x - Noise Control D25 + ACE @CPU clock 80MHz Driving Innovations™ 22
Slide 25: Conclusion
Conclusion • TWS solution using Andes D25+ACE • New idea of how to design a SOC • Andes V5 role in the TWS platform • Example of ANC customized instruction using ACE Driving Innovations™
Slide 26: Thank you, See you next webinar!
Sl a * es . at RISC-V CON - 7 2 ‘-” @5 8 e * — FZ F Ves 6 @ » { 2. 2 we 1 ¢ eo a f Ss © SS X\ . 4 . . o ‘ . Thank you, See you next webinar!