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Andes Technology — Andes Infuses into Artificial Intelligence webinar (July 2020)

22 slides from Andes Technology's conference presentation, Jul 9, 2020

  1. Slide 1: Andes Infuses into Artificial Intelligence

    Andes Infuses into Artificial Intelligence High-Efficiency and High-Flexibility Processor IPs + NN SDK for AI Simon Wang Technical Marketing Manager Andes Technology July 9, 2020

  2. Slide 2: Agenda

    Agenda  The Diversity of AI Use-Cases  Andes RISC-V Processors for AI  Andes NN SDK for AI  Summary Taking RISC-V® Mainstream 2

  3. Slide 3: Andes at A Glance

    Andes at A Glance Who We Are RISC-V Founding Taiwan Stock CPU Pure-play CPU IP Company Premier Member Exchange Listed Running Task Groups Major Open-Source Vice Chair of TSC Contributor/Maintainer Director of the Board RISC-V Ambassador Quick Facts 15 200+ 80% FR NL BJ KR years old Licensees R&D USA

  4. Slide 4: The Diversity of AI Use-Cases

    The Diversity of AI Use-Cases Vision Voice and Speech Any signal • Image classification • Audio front-end processing • Sensor fusion with force, • Object detection • Keyword spotting pressure, accelerometer, • Image segmentation • Voice command gyro, ampere meter, • Spoof detection • Speech to text

  5. Slide 5: Andes Processors to Fit Your AI

    Andes Processors to Fit Your AI Data center Automotive Mobile AR/VR Surveillance • ADAS, HDR • > 10 cameras Smart Home • Face unlock V-Series CPUs • Bokeh Smart Camera • Avatar • Intelligent HMI • Gesture recognition SLAM Smart IoT Devices • Barge-in • • Beamforming • High resolution • Speech to tex

  6. Slide 6: Andes RISC-V Processors Family

    Andes RISC-V Processors Family N-Series D/A-Series V-Series Baseline DSP/SIMD Vector RISC-V baseline 32/64-bit SMP RISC-V baseline 32/64-bit SMP RISC-V baseline 64-bit Andes V5 instructions Andes V5 instructions Andes V5 instructions (RV-EIMACFD-XV5) DSP/SIMD instructions (RVP) Vector instructions (

  7. Slide 7: RVP and RVV for Data Computation

    RVP and RVV for Data Computation RISC-V DSP/SIMD P-ext RISC-V Vector V-ext • Andes contributed market-proven • Follow RVV latest standard RISC-V Baseline DSP/SIMD to RVP • >300 vector instructions • Use RV32 and RV64 XLEN-bit GPRs • SIMD with 8b, 16b, 32b • Scalable vector registers • Clean state •

  8. Slide 8: Typical Andes CPU Usages for AI from Edge to Cloud

    Typical Andes CPU Usages for AI from Edge to Cloud Best-fitting MCU edge AI Performance edge AI Cloud AI control logic • Single MCU with small • Application SoC for large • Heterogeneous and cluster • RISC-V Compact and data computation (e.g. data process of CV/ML computing for AI data center modula

  9. Slide 9: Efficiency Boost with Andes Custom Extension

    Efficiency Boost with Andes Custom Extension™ Compute kernel functions Control ports Streaming ports + compute kernel functions + control ports • Extend instructions for kernel • Extend instructions to control functions (e.g. CONV, GEMM) ports (e.g. send command, ack, • Extend instructions for high

  10. Slide 10: Voice-Based Human Machine Interface Use Case

    Voice-Based Human Machine Interface Use Case Simple neural network model Pre-Processing Feature extraction Voice trigger • Echo cancellation • FFT • Keyword spotting • Noise reduction • Mel-Frequency (always-on) • Beamforming Cepstral Coefficients wakeup • Auto gain control • Filter bank • … • … Spe

  11. Slide 11: Voice-Based Human Machine Interface Use Case

    Voice-Based Human Machine Interface Use Case Simple neural network model Pre-Processing Feature extraction Voice trigger Language processing • Echo cancellation • FFT • Keyword spotting • Natural Language • Noise reduction • Mel-Frequency (always-on) Processing • Beamforming Cepstral Coefficients •

  12. Slide 12: Deep Learning Chipset Global Market

    Deep Learning Chipset Global Market  Deep learning chipset market growing at 42.2% CAGR from 2016 to 2025  Largest growth coming from ASIC including: • CPU • DSP • VPU (Vector processing unit) • Hard-wired engine • … Tratica, March, 2017 https://tractica.omdia.com/newsroom/press-releases/deep-lear

  13. Slide 13: Andes NN SDK

    Andes NN SDK Full ecosystem of AI software frameworks, compilers and libraries AI applications Signal processing AI frameworks AI model optimization AI inference engine AI compiler Andes DSP library Andes NN library LLVM compiler Andes NN SDK AndesCore™ baseline, RVP, RVV, ACE N-Series, D/A-Series,

  14. Slide 14: Andes DSP Library

    Andes DSP Library  Optimized low-level DSP functions for RISC-V baseline and RVP processors  Boost signal processing performance  >200 functions in 8 categories  CMSIS-DSP like APIs Speedup of RV64P over baseline1 12 10.81x 10 8 6 4 Average 2.5x 2 Maximum 0 1: based on 25-Series, FPGA Taking RIS

  15. Slide 15: NN Library and TensorFlow Lite Micro

    Andes NN Library and TensorFlow Lite Micro AI frameworks Andes NN library • An optimized low-level NN functions for RISC-V baseline, TFLiteμ RVP and RVV processors Hookup kernel • Boost NN performance by using SIMD and vector Andes NN library instructions Depthwise Convolution • CMSIS-NN like API Co

  16. Slide 16: RVP DSP/SIMD Processors Speedup

    RVP DSP/SIMD Processors Speedup Speedup of RVP over baseline1 The higher the better compiler auto-gen MP3 decode 1.95x RV32P AMR voice codec 3.67x RV64P ML-KWS (Keyword Spotting) 8.86x PNET (90% of Face Detection) 8.87x CIFAR-10 (Image Classification) 14.32x  Performance boost with 0 2 4 6 8 10 12

  17. Slide 17: RVV Vector Processors Speedup over Baseline

    RVV Vector Processors Speedup over Baseline SGEMM 57x Q7 filtering 39x F32 filtering 19x Pointwise CNN 21x Depthwise CNN 18x RGB CNN 18x F32 basic mathematics 19x 0 10 20 30 40 50 60 Note • Compared to pure C scalar code compiled with high optimization • Both vector and scalar code ran on the NX27V

  18. Slide 18: Andes KWS Solution

    Andes KWS Solution https://arxiv.org/pdf/1711.07128.pdf  Voice trigger • To wakeup the system • Consume lower power than ASR for always-on usage • Reduce false alarms Voice Input Feature Extraction NN Inference  Voice command • Hands-free solutions • Simple and offline HMI ADP-XC7K Taking RISC-V®

  19. Slide 19: Andes KWS Solution

    Andes KWS Solution  KWS software stack • Andes NN/DSP library accelerated by Andes RISC-V DSP/SIMD P-ext  KWS application • Feature extraction: MFCC Model DS-CNN DNN GRU • AI model: DNN, DS-CNN, GRU Accuracy 94.4% 84.6% 93.5%  KWS tools Storage size 186 KB 243 KB 243 KB (code+rodata+data) • KWS T

  20. Slide 20: Andes Partners for AI

    Andes Partners for AI AI tools and IP Open Source SW DSP, Audio and Vision Development tools Taking RISC-V® Mainstream 20

  21. Slide 21: Summary

    Summary  Andes RISC-V processors support the diversity of AI use-cases • Baseline: compact and modular control logic • Baseline + RVP: efficient DSP/SIMD for simple data computation • Baseline + RVV: high performance, efficiency and configurability to enable data intensive computing from edge to cl

  22. Slide 22: Thank you, See you next webinar!

    Thank you, See you next webinar!

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