Slide 1: Introduction to Memory
Introduction to Memory Reviewed: 2025 © 2020-2025 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Statements regarding products, including s
Slide 2: Copyright guidelines
Copyright guidelines By using any content provided by the Micron Educator Hub, you acknowledge that Micron Technology, Inc. (“Micron”) is the sole owner of the content and agree that any use of the content provided by the Micron Educator Hub must comply with applicable laws and require strict compli
Slide 3: How to cite sources from the Micron Educator Hub
How to cite sources from the Micron Educator Hub • Micron is committed to collaborate with Educators to Use case How to cite sources make semiconductor memory education resources available through the Micron Educator Hub. a) Whole slide deck or whole document No additional citation required. • The c
Slide 4: Table of Contents
Table of Contents 1 Goal, Objectives and Target Audience 2 Introduction to Semiconductor Memory 3 Semiconductor Devices Overview 4 Introduction to DRAM 5 Introduction to Flash 6 Key Terminology/Glossary 7 Document Updates 4
Slide 5: Introduction to Memory - Goal and Objectives
Introduction to Memory - Goal and Objectives Participants will be able to understand basic concepts of semiconductor memory technologies. Objectives: 1. Explain what is Semiconductor Memory 2. Describe some of the fundamental semiconductor devices used in memory (resistor, diode, capacitor, transist
Slide 6: Introduction to Memory - Target Audience
Introduction to Memory - Target Audience • This Introduction to Memory module covers the basic structure and operation of DRAM and Flash memory • Interns, NCGs (New College Grads), and new employees in technical roles need to understand these concepts • Examples of critical target audience roles at
Slide 7: 2. Introduction to Semiconductor Memory
2. Introduction to Semiconductor Memory 7
Slide 8: Types of Semiconductor Devices
Types of Semiconductor Devices LOGIC DEVICES MEMORY DEVICES SPECIALTY DEVICES CPU (Central Processing Unit) GPU (Graphics Processing Unit) DRAM CPU (under fan) DRAM CMOS Image Sensors Memory Cards Flash GPU (under fan) NAND NOR LEDs NAND SSD MICRON Products CPUs can have GPU cores integrated on same
Slide 9: Logic vs Memory
Logic vs Memory LOGIC MEMORY • A logic chip performs a function on given data • A memory chip allows you to store & retrieve data • A processor or controller chip • A chip that holds programs and data (temporarily or • Logic implies "processing" permanently) • a fixed operation is performed • DRAMs
Slide 10: Basic Memory Operations
Basic Memory Operations WRITE OR READ ERASE PROGRAM WRITE or PROGRAM or READ information from the ERASE or delete information store information (1s and 0s) memory from the memory in the memory Example: Snap a picture Example: You look at a Example: You don’t like the with a phone. The picture pictur
Slide 11: How Memory Works – Binary language
How Memory Works – Binary language • Electronic systems store information using digital technology • Digital technology uses BITs and BYTEs to encode information (1 BYTE = 8 BITs) • Each BIT is a single piece of information that can have one of two values: 0 or 1 • Groups of BITs are used to represe
Slide 12: Memory Storage
Memory Storage • Memory (data) storage is not a modern invention. • Over the years many different approaches have been used to store information… 1725 1930 1940 1950 1960 1970 1980 1990 2000 2010 2020 Future Punched tape 1725 – 1990 Punched cards 1890 – 2000 Magnetic Tape Magnetic 1928 – Present Har
Slide 13: Memory Storage Methods
Memory Storage Methods Magnetic Optical Charge Resistance Hard Disk Drive 1 0 1 1 0 1 0 1 Read head senses changes in direction of domains within the thin magnetic film: change = 1, no change = 0 (binary code for “µ”) 13
Slide 14: Memory Storage Methods
Memory Storage Methods Magnetic Optical Charge Resistance CD ROM, DVD, Blu-Ray Compact Digital Video Blu-Ray Disc CD ROM Disc Disc 780nm Red Laser DVDLaserRed 650nm 405nm Blue Laser Blu-Ray Track pitch Track pitch Track pitch 1.6µm 0.74µm 0.30µm CD DVD Blu-Ray Storing Binary 1’s and 0’s with indenta
Slide 15: Memory Storage Methods
Memory Storage Methods Magnetic Optical Charge Resistance DRAM NAND Flash + Storing Binary 1’s and 0’s based on + + how much charge is kept in the + storage node + + Storage Node + + Storage Node 15
Slide 16: Memory Storage Methods
Memory Storage Methods Magnetic Optical Charge Resistance Cross-Point Storage Node Electrical Current Storing Binary 1’s and 0’s based on how much resistance there is to current flowing through the storage node 16
Slide 17: Major Types of Memory
Major Types of Memory • Memory can be classified as Volatile or Non-Volatile • Volatile (example: DRAM) • Memory that will lose stored information when power is removed from the part • Non-Volatile (example: NOR & NAND Flash) • Memory that will retain stored information even when power is removed fr
Slide 18: Summary of Silicon-Based Memory Technologies
Summary of Silicon-Based Memory Technologies Short Full Name Description Type Speed Density Primary Applications Name SRAM Static Random Data is stored as the state of a Volatile Very Fast Read Low Cache between CPU and Access Memory digital flip-flop. Does not require and Write other memory types.
Slide 19: Comparison of Memory Types
Comparison of Memory Types Power Consumption Write Speed Read Speed Cost per Bit Magnetic SRAM SRAM $ SRAM Power Consumption Hard drive Read Speed Write Speed DRAM Cost per Bit DRAM NOR SRAM NAND NOR DRAM DRAM NOR NAND NAND NOR Magnetic Magnetic Magnetic NAND Hard drive Hard drive Hard drive Lower i
Slide 20: DRAM (DDR, LPDDR, GDDR & HBM)
DRAM = Dynamic Random Access Memory DDR = Double Data Rate LPDDR = Low Power Double Data Rate DRAM (DDR, LPDDR, GDDR & HBM) GDDR = Graphics Double Data Rate HBM = High Bandwidth Memory Automotive Personal Smartphone Data Center PC Gaming Game Console ADAS Computing Content • High-performance volatil
Slide 21: Flash Memory (NAND and NOR)
ADAS = Advanced Driver Assistance Systems AI = Artificial Intelligence AR = Augmented Reality Flash Memory (NAND and NOR) IoT = Internet of Things VR = Virtual Reality Automotive Personal Portable Smartphone Data Center Game Console ADAS Computing Storage Video • Long-term memory storage AR/VR Surve
Slide 22: 3. Semiconductor Devices Overview
3. Semiconductor Devices Overview Fundamentals | Capacitors | Transistors 23
Slide 23: Conductors, Insulators & Semiconductor Materials
Conductors, Insulators & Semiconductor Materials Conductors • Allow electrical current to flow easily • Conductors used in integrated circuits are mostly metals: Aluminum, Tungsten and Copper Insulators • Very resistive to electrical current flow • Used to electrically isolate one part of the circui
Slide 24: Resistivity Scale
Resistivity Scale • Electrical resistivity is a measure of how strongly a material opposes the flow of electric current. • Low resistivity indicates a material that readily allows the movement of electrical charge. Resistivity () .cm 10-20 10-15 10-10 10-5 100 105 1010 1015 1020 { { { Conductors I
Slide 25: Semiconductor Doping
Semiconductor Doping Intrinsic Si Intrinsic (pure) Silicon – Very resistive to electrical current flow – Intrinsic silicon has very few applications in memory chips – Silicon has 4 valence electrons (in outer shell) Doped Silicon N-Type Si – A small percentage of impurities (“dopants”) are added to
Slide 26: Important Semiconductor Components
Important Semiconductor Components • Resistors • Diodes • Reduces or limits current flow • Allows current to flow in one direction p n • Can be used to electrically isolate adjacent devices from each other • Capacitors • Transistors • Stores an electrical charge • Controls current flow • Has two con
Slide 27: Resistors
Resistors Definition: A device that reduces or limits current flow • A resistor is created by using a material less conductive (more resistive) anywhere along the path of current flow • Resistors can have a fixed or variable resistance value Voltage Divider Circuit R1 R2 Vout = Vin (R2 / R1+R2) Vin
Slide 28: Capacitors
Capacitors Definition: An electronic device used to store electric charge • A capacitor consists of: • Two conductive “plates” – we arbitrarily call them “top” and “bottom” plates • An insulating layer known as a “dielectric” that electrically separates the two plates • Opposite charges on the plate
Slide 29: Capacitors
Capacitors • If a capacitor is hooked up to a power source, such as a battery, the capacitor will “charge up” until it can hold no more charge • Analogy: This is like filling a bucket with water until it can hold no more water + – 3/4 + – + – + – charge capacitor + time electrons _ battery 30
Slide 30: Capacitors
Capacitors • When the battery is disconnected, the capacitor will gradually begin to lose the charge. This is known as “discharging”. • Analogy: This is like water slowly leaking out of small holes in a bucket + – 3/4 + – + – + – charge capacitor + time _ battery 31
Slide 31: Capacitors
Capacitors How much charge can a capacitor hold? C ≈ k x plate area / spacing • As the surface area of the conductive plates is increased, the capacitor can hold more charge • Note: The plates do not have to be flat! – + + – – + + – • The amount of charge or energy storage in a capacitor is called t
Slide 32: Into the Z Dimension!
Into the Z Dimension! If we make the capacitor X x Y larger we cannot achieve higher die density on wafer Current cylindrical “containers” have a So maintain same height ~40x their X x Y on wafer but diameter “footprint” go vertical on wafer! 33
Slide 33: Capacitors
Capacitors How much charge can a capacitor hold? C ≈ k x plate area / spacing • As the spacing between the plates decreases, the capacitor can hold more charge. This spacing can also be thought as the dielectric thickness. • The choice of dielectric material can also increase the amount of charge th
Slide 34: Diodes
Diodes Definition: An electronic device that allows current to flow in one direction only • Formed by connecting a P-type material with an N-type material Schematic symbol for a diode p n Simplified physical structure of a diode + - Forward biased: Current flows Diodes P side N side Reverse biased:
Slide 35: Diodes
Diodes • Diodes can be used to electrically isolate adjacent devices from each other • In the example below, the P-Well and N-Well form a diode where they meet • By applying a negative voltage to the P-Well and a positive voltage to the N-Well, the diode is reverse-biased, and current cannot flow be
Slide 36: Transistors
Transistors Definition: An electronic device that can control the current running though it – like an On/Off switch • The most common type is the Field Effect Transistor (FET) • Used in digital applications • Low-power device • Still being scaled below 10 nm Substrate Circuit symbol of a Structure o
Slide 37: MOSFET Overview
MOSFET Overview Structure of a MOSFET • Doped semiconductor (silicon) substrate • Doped source and drain regions (oppositely doped from substrate) • Insulating gate oxide • Metal control gate on top of oxide is used to apply voltages that turn the transistor ON or OFF • The “channel” is the region b
Slide 38: MOSFET Overview
MOSFET Overview OFF STATE Control Gate Voltage = -3V • Drain voltage is higher than source voltage, creating a voltage drop. Current could flow through the device under Drain Voltage = +3V these conditions if the gate allows. Source Voltage = 0V • Negative voltage applied to the control gate attract
Slide 39: MOSFET Overview
MOSFET Overview ON STATE Control Gate Voltage = +3V • Drain voltage is higher than source voltage, creating a voltage drop. Current could flow through the device under Drain Voltage = +3V these conditions if the gate allows. Source Voltage = 0V • Positive voltage applied to the control gate attracts
Slide 40: MOSFET States: OFF and ON Summary
MOSFET States: OFF and ON Summary Control Gate Voltage = -3V Control Gate Voltage = +3V Drain Drain Source Voltage Source Voltage Voltage +3V Voltage +3V 0V 0V OFF STATE ON STATE 41
Slide 41: MOSFET Transistor Dimensions
MOSFET Transistor Dimensions Three Important Dimensions (but many others!): • Gate Length (LG): As the gate length (channel) gets shorter, the device can switch faster. The tradeoff is an increase of leakage current in the off-state. • Gate Width (WG): As the gate gets wider, more current can flow f
Slide 42: 4. Introduction to DRAM
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Slide 43: Basic DRAM Memory Cell
Basic DRAM Memory Cell • Shown on this slide is all that is needed to store a single “bit” (1 or 0) of digital information on a DRAM • Each cell consists of one transistor and one capacitor. • A DRAM chip has billions of these “cells” top plate dielectric bottom plate Capacitor (“container”): • Used
Slide 44: DRAM Operation – Write
DRAM Operation – Write 1. Bit Line delivers positive voltage to the source of the transistor. bottom plate top plate dielectric Capacitor Word Line: Bit Line: Gate source drain Transistor P well 45
Slide 45: DRAM Operation – Write
DRAM Operation – Write 1. Bit Line delivers positive voltage to the source of the transistor. 2. Word Line delivers positive voltage to the gate, which creates the channel and turns it ON. bottom plate top plate dielectric Capacitor Word Line: Bit Line: Gate source drain Transistor channel P well 46
Slide 46: DRAM Operation – Write
DRAM Operation – Write 1. Bit Line delivers positive voltage to the source of the transistor. 2. Word Line delivers positive voltage to the gate, which creates the channel and turns it ON. bottom plate 3. Bit Line voltage passes through the source and drain to the top plate dielectric capacitor. Cap
Slide 47: DRAM Operation – Write
DRAM Operation – Write 1. Bit Line delivers positive voltage to the source of the transistor. 2. Word Line delivers positive voltage to the gate, which creates the channel and turns it ON. + – – + + – – + bottom plate 3. Bit Line voltage passes through the source and drain to the + – – + – – top pla
Slide 48: DRAM Operation – Write
DRAM Operation – Write 1. Bit Line delivers positive voltage to the source of the transistor. 2. Word Line delivers positive voltage to the gate, which creates the channel and turns it ON. + – – + + – – + bottom plate 3. Bit Line voltage passes through the source and drain to the + – – + – – top pla
Slide 49: DRAM Operation – Read
DRAM Operation – Read 1. Word Line delivers positive voltage to the gate, which creates the channel and turns it ON. + – – + + – – + bottom plate + – – + – – top plate dielectric + + + – – + Capacitor + – – + + – – + + – – + Word Line: + – – + + + Bit Line: Gate source drain Transistor channel P wel
Slide 50: DRAM Operation – Read
DRAM Operation – Read 1. Word Line delivers positive voltage to the gate, which creates the channel and turns it ON. 2. Charge on capacitor passes from drain to source and onto + – – + the Bit Line. + – – + bottom plate + – – + – – top plate dielectric + + + – – + Capacitor + – – + + – – + + – – + W
Slide 51: DRAM Operation – Read
DRAM Operation – Read 1. Word Line delivers positive voltage to the gate, which creates the channel and turns it ON. 2. Charge on capacitor passes from drain to source and onto the Bit Line. bottom plate top plate dielectric 3. Charge on capacitor is (temporarily) lost. Capacitor Word Line: Bit Line
Slide 52: DRAM Operation – Read
DRAM Operation – Read 1. Word Line delivers positive voltage to the gate, which creates the channel and turns it ON. 2. Charge on capacitor passes from drain to source and onto the Bit Line. bottom plate top plate dielectric 3. Charge on capacitor is (temporarily) lost. Capacitor 4. Sensing circuits
Slide 53: DRAM Operation – Read
DRAM Operation – Read 1. Word Line delivers positive voltage to the gate, which creates the channel and turns it ON. 2. Charge on capacitor passes from drain to source and onto + – – + the Bit Line. + – – + bottom plate + – – + – – top plate dielectric 3. Charge on capacitor is (temporarily) lost. +
Slide 54: Read (& Refresh)
Read (& Refresh) Word Line Bit Line Word Line turns ON WL ON Vccp Vccr “1” Sense Amp Reads a “1” Ready to Read Charge from Capacitor Ready for next Read Vccr/2 “0” Ground Sense Amp Reads a “0” Container depth ~1um human hair ~70um 3D Model of a DRAM Array 55
Slide 55: Evolution of DRAM
Evolution of DRAM 2022 2020 Up to 128Gb 2014 16Gb DRAM 2002 8Gb DRAM 1β Micron’s Next 1992 1Gb DRAM 1α Micron’s World’s Most Advanced DRAM Process 1987 16Mb DRAM World’s Most Advanced Technology (in 2022) 1981 1Mb DRAM 41 years 2,000,000x density increase DRAM Process Technology (in 2020) 64K DRAM 5
Slide 56: DRAM Scaling Trend
DRAM Scaling Trend With each generation, by reducing the feature sizes of our memory cells on each die we can increase density, achieve higher bits per wafer, and lower cost per bit. Bits/wafer DRAM Minimum Feature size 57
Slide 57: From Micron Investor Day 12 May 2022
1β = name of a Micron DRAM technology CY = Calendar Year DRAM = Dynamic Random Access Memory DDR = Double Data Rate Gb = Gigabit HBM = High Bandwidth Memory LPDDR = Low Power Double Data Rate From Micron Investor Day 12 May 2022 58
Slide 58: 24GB HBM3 Gen2 with 1Beta 24Gbit DRAM die
This 24GB HBM3 Gen2 contains 8 of the leading-edge 1Beta 24Gbit DRAM die! Those HBM3- specific die are interconnected vertically by Thru-Silicon Vias (TSVs) that are formed in the wafer during in-fab processing From Micron News Release 26Jul23 LINK 59
Slide 59: 5. Introduction to Flash
5. Introduction to Flash micron.
Slide 60: Structure of a Basic Flash Cell
Structure of a Basic Flash Cell Dielectric – insulator Control Gate – where a controlling voltage is applied Floating Gate – conducting or semi- conducting layer that is surrounded by a dielectric used to store charge and alter the threshold voltage of the device. This is the “storage node” of the N
Slide 61: NAND Function
NAND Function • High voltage on the Control Gate causes electrons to tunnel through the gate oxide and get trapped within the Floating Gate ++++++++++++ - -- -- ---- - ----- - -- -- ---- - ----- - -- ----- - - - - - - - - - - -- -- -- -- -- - - - - - - - - - - Source Drain e- 62
Slide 62: Programming / Writing a NAND Cell
Programming / Writing a NAND Cell • Ground the substrate • Apply ~+20V to the control gate • Electrons in the substrate tunnel through the gate oxide and relocate in the floating gate • When voltage is released, electrons are trapped in the floating gate making NAND Flash a non-volatile memory • For
Slide 63: Erasing a NAND Cell
Erasing a NAND Cell • Ground the control gate • Apply ~+20V to the substrate • Electrons trapped within the floating gate tunnel back through the gate oxide into the substrate Source Drain 20V 64
Slide 64: Reading a NAND Cell
Reading a NAND Cell VREAD = 3.0 V Reading a Programmed Cell: • 0.5V on drain, 0V on source create a voltage drop • VREAD = 3.0V on the control gate attempts to create a channel to 0V 0.5 V +++++++++++++ turn transistor ON - -- -- ---- • Electrons trapped in the floating gate prevent the channel from
Slide 65: Flash Function: Logic States
Flash Function: Logic States # of e- Trapped in Cell Threshold State of the Cell Current in Channel Logic State Floating Gate Voltage Low Low Not Programmed Yes 1 High High Programmed No 0 66
Slide 66: NAND Flash vs. NOR Flash
NAND Flash vs. NOR Flash Bit Line (BL) NAND SGS WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 SGD ▪ Higher Density but Slower Shared Select Gate Source (SGS) and Bit Line connections for a string of NAND Flash Memory Cells BL Source SGS WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 SGD N-Gnd N N N N N N N N N N-BL P Bit Line (
Slide 67: Multi Level Cell (MLC) Technology
Multi Level Cell (MLC) Technology • So far we have seen a NAND cell that can store 1 bit per cell where the cell is in one of two possible states: • Programmed (Logic 0) or cup is full • Erased (Logic 1) or cup is empty • Continuous innovations in NAND technology now allow us to store more than 1 bi
Slide 68: Multi Level Cell (MLC) Technology
Multi Level Cell (MLC) Technology • So far we have seen a NAND cell that can store 1 bit per cell where the cell is in one of two possible states: • Programmed (Logic 0) or cup is full • Erased (Logic 1) or cup is empty • Continuous innovations in NAND technology now allow us to store more than 1 bi
Slide 69: Micron 2018 Analyst & Investor Event
MLC = Multi Level Cell (2 bits per cell) QLC = Quad Level Cell (4 bits per cell) SLC = Single Level Cell (1 bit per cell) SSD = Solid State Drive Tb = Terabit (one trillion bits or 1,000 gigabits) TLC = Triple Level Cell (3 bits per cell) Micron 2018 Analyst & Investor Event 70
Slide 70: Charge States in NAND SLC/MLC/TLC/QLC Memory
Charge States in NAND SLC/MLC/TLC/QLC Memory QLC - Quad Level Cell 16 Charge States: 1 Erased + 15 Programmed 4 Bits per cell L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 VTH TLC - Triple Level Cell 8 Charge States: 1.3x capacity increase 1 Erased + 7 Programmed 3 Bits per cell L0 L1 L2 L3
Slide 71: 2D NAND of Years Past
2D NAND of Years Past • Early NAND generations arranged the cells horizontally Source Memory Cell Memory Cell Memory Cell Drain Select Memory Cell Select Gate Gate Source Drain Programed Erased Programmed Programmed Programmed NAND String 72
Slide 72: Into the Z Dimension!
Into the Z Dimension! The 2D string of NAND memory cells requires more X x Y area if we expand for higher density (more cells per string) We can increase density by going to 3D to leverage the vertical direction through the implementation of many “tiers” of memory cells 73
Slide 73: 3D NAND
3D NAND Drain • By standing the string cells on end and enabling completely new and innovative designs, processes, and methods we can achieve increasing memory densities within a given X x Y area on the wafer. Only ~38 tiers shown in this SEM 3D Model of a 3D NAND Array Stacked tiers ~10um human hai
Slide 74: NAND Scaling Trend
Micron’s World’s First NAND Scaling Trend 176 Tier 3D NAND! 512Gb 2D NAND X, Y “Footprint” Scaling needed to gain higher density for each new generation 3D NAND X, Y “Footprint” Scaling could be relaxed due to gain in density by adding vertical tiers BL = Bit Line Gb = Gigabits WL = Word Line 75
Slide 75: Micron Ships the Industry's First 176-Layer QLC NAND
January 11, 2022 Micron Ships the Industry’s First 176-Layer QLC NAND in Volume and Unveils the 2400 PCle Gen4 Client SSD This 2TB SSD contains 16 of the 176-layer 1Tb die! I/O speed = Input/Output speed PCIe = Peripheral Component Interconnect Express QLC = Quad Level Cell (4 bits per cell) SSD = S
Slide 76: CuA – CMOS Under Array
*CuA – CMOS Under Array - another Micron innovation – by locating all support circuitry underneath the memory cell tiers, the die size can be further minimized, thereby gaining even higher bit density (like all supporting utilities and parking garage installed beneath a skyscraper!) CuA = CMOS Under
Slide 77: From 30Jul24 Micron Press Release
From 30Jul24 Micron Press Release LINK 78
Slide 78: 6. Key Terminology/Glossary
6. Key Terminology/ Glossary 79
Slide 79: Terminology: wafer, die, array, periphery, scribe
Terminology: wafer, die, array, periphery, scribe • Memory is fabricated on a 300 mm diameter silicon wafer. We try to maximize our die per wafer. • A die is the memory chip which has a memory array and a periphery • The array (DRAM cells or NAND cells) stores information • The periphery has many ci
Slide 80: Glossary
Glossary Term or Acronym Definition/Description Array The die has a memory array and a periphery. The memory array is where the data (1s and 0s) is stored. Capacitor An electronic device used to store electric charge. A capacitor consists of two conductive “plates” and an insulating layer known as a
Slide 81: Glossary
Glossary Term or Acronym Definition/Description MOSFET Metal Oxide Semiconductor Field Effect Transistor. A low-power electronic transistor device used in digital applications. NAND This is one of the types of semiconductor Flash memory that Micron designs and fabricates. In NAND memory data is stor
Slide 82: Glossary
Glossary Term or Acronym Definition/Description SLC Single Level Cell. In NAND Flash, it refers to a NAND architecture that allows to program only 1 bit per memory cell. Silicon, doped A small percentage of controlled impurities or dopants are added to the silicon to reduce its resistance. Silicon,
Slide 83: 7. Document Updates
7. Document Updates 84
Slide 84: Document Updates
Document Updates Date Description January 2025 • Added goals, objectives and target audience • Added several new images • Added acronym legends • Added glossary section 85
Slide 85: provided on an “AS IS” basis without warranties of any kind. Statements regarding products,
© 2020–2025 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Statements regarding products, including statements regarding product features,