Slide 1: MOS Transistor (MOSFET) Device Physics
MOS Transistor (MOSFET) Device Physics Reviewed 2025 © 2022-2025 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Statements regarding produc
Slide 2: Copyright guidelines
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Slide 4: Device Physics Module Sequence
Device Physics Module Sequence 1. Semiconductor fundamentals & PN junction device physics - Energy band diagram, fermi-level, density of states, doping, PN junction 2. MOS Capacitor (MOSCAP) - MOS electrostatics, ideal CV, non-idealities, key parameter extractions 3. MOS Transistor (MOSFET) - Channe
Slide 5: Table of Contents
Table of Contents 1 Goals, objectives and target audience 2 MOSFET IV characteristics 3 MOSFET band diagrams at different biasing conditions 4 MOSFET Non-Ideal Effects I. Subthreshold Leakage II. Drain Induced Barrier Lowering (DIBL) III. Gate Induced Drain Leakage (GIDL) 5 Glossary 6 References 5
Slide 6: Device Physics: MOSFET – goal and objectives
Device Physics: MOSFET – goal and objectives Goal Objectives • Provide a foundational understanding of MOSFET • Illustrate the architecture and operations of and its electrical characteristics MOSFET • Interpret and draw band-diagram for different material systems and operating conditions • Understa
Slide 7: Target Audience
Target Audience • Interns, NCGs (new college grads) and new employees in some technical roles need to understand these concepts Pro tip • Examples of critical target audience roles at Micron that utilize Everyone interviewing at Micron can these concepts use this presentation to prepare for – Device
Slide 8: MOSFET IV Characteristics
MOSFET IV Characteristics 8
Slide 9: MOSFET
MOSFET • MOSFET stands for Metal Oxide Semiconductor Field Effect Transistor • MOSFET is a four-terminal device n-channel (NMOSFET) p-channel (PMOSFET) Gate Gate Source Metal Drain Source Metal Drain G G Oxide Oxide N+ N+ P+ P+ P-sub N-sub S D S D B B Body Body • CMOS is Complementary MOSFET uses bo
Slide 10: MOSFET
MOSFET Gate VGS Source D Drain • Source is grounded together with bulk Metal VDS Oxide • Hence typically there are two potential of interest, VGS N+ IDS N+ and VDS P-sub • In terms of current, there is no IGS as there is oxide in between metal and semiconductor, we are interested in IDS that flows b
Slide 11: MOSFET Threshold Voltage, VT
MOSFET Threshold Voltage, VT Refer to slide #14-20, MOSCAP - Part 2 document for detailed descriptions Accumulation Depletion 𝜑𝑠 =2∅𝑏 Strong Inversion 𝝋𝒔 0 Threshold = Onset of strong inversion (channel is inverted from p- type to n-type, electron concentration at surface equals holes…
Slide 12: MOSFET IV Characteristics
MOSFET IV Characteristics VGS = 0 VGS > VT Source VDS = 0 Source VDS = 0 D D Metal Metal Oxide Oxide N+ N+ N+ N+ P-sub P-sub Body Body Depletion region • Depletion regions at PN junctions blocks • Channel is formed (inverted to n-type at any current flow surface) • Regardless, there will be no curre
Slide 13: ID-VG Characteristics VGS < VT
ID-VG Characteristics VGS < VT Source D VDS = 0 Metal IDS Oxide N+ N+ N+ N+ P-sub Body VGS < VT • No channel formation 𝑄𝐼𝑛𝑣 = −𝐶𝑂𝑥 (𝑉𝐺 − 𝑉𝑇 ) Gate Overdrive, inversion charge forms only VDS when there is net gate overdrive 13
Slide 14: ID-VG Characteristics VGS > VT, low VDS
ID-VG Characteristics VGS > VT Source VDS (Low) > 0 D Metal IDS Oxide N+ N+ N+ P-sub Body Low VDS: • Ohmic/Linear region (thin sheet of conductor) • MOSFET acts as a resistor, follows Ohms law (V=IR) VDS 14
Slide 15: ID-VG Characteristics VGS > VT, moderate VDS
ID-VG Characteristics VGS > VT Source VDS > 0 D Metal IDS Oxide N+ N+ N+ P-sub Body Moderate VDS: • Potential is increasing from S→D • Drain side is increasingly reverse biased, depletion region width increases from S→D • IDS will increase but not at the same rate as before 𝑉𝐷𝑆 ↑ VDS 𝑄𝑀 =…
Slide 16: ID-VG Characteristics: pinch-off
ID-VG Characteristics VGS > VT Source VDS > 0 At source side D 𝑉𝐺𝑆 - 0 > 𝑉𝑇 Metal IDS Oxide At Drain side, when VDS reaches certain value, VDS,sat N+ N+ N+ 𝑉𝐺𝑆 - 𝑉𝐷𝑆 = 𝑉𝑇 P-sub 𝑉𝐷𝑆 = 𝑉𝐷𝑆,𝑠𝑎𝑡 = 𝑉𝐺𝑆 - 𝑉𝑇 Body High VDS (Pinch-off point): • When 𝑉𝐷𝑆 = 𝑉𝐺𝑆 - 𝑉𝑇…
Slide 17: ID-VG Characteristics: very high VDS
ID-VG Characteristics VGS > VT Source VDS > 0 D Metal IDS Oxide N+ N+ N+ P-sub Body Very high VDS : • When 𝑉𝐷𝑆 > 𝑉𝐺𝑆 - 𝑉𝑇 , channel formation further reduces, channel current does not increase further, reaches saturation VDS |𝑄𝑀 | = 𝑄𝐼𝑛𝑣 ↓+ 𝑄𝐷𝑒𝑝 ↑ 17
Slide 18: Why channel current saturates?
Why channel current saturates? • Current is controlled by the rate of electron emission from the source into the channel • Electrons are swept by large electric field at pinch off/depletion region • Current becomes independent of drain voltage in the saturation region electrons Ec Low VDS Ev High VD
Slide 19: ID-VG Characteristics
ID-VG Characteristics IDS linear region saturation region Linear (triode) region 𝑉𝐷𝑆 < 𝑉𝐺𝑆 - 𝑉𝑇 𝑉𝐺𝑆3 Saturation region 𝑉𝐷𝑆 > 𝑉𝐺𝑆 - 𝑉𝑇 Increasing VGS 𝑉𝐺𝑆2 𝑉𝐺𝑆1 VDS 19
Slide 20: ID-VG Characteristics
ID-VG Characteristics IDS Increasing VDS VGS 20
Slide 21: Flat Band
Gate Flat Band VGS = 0V, VDS = 0V Source Drain Metal Oxide X-Dir N+ N+ P-sub EC Ei Y-Dir Ef Body EV Y-Dir X-Dir 𝜑s = 0 Large barrier for electrons to diffuse 21
Slide 22: Accumulation
Gate Accumulation VGS < 0V, VDS = 0V Source Drain Metal Oxide X-Dir N+ N+ P-sub q𝝋s EC q𝝋s Ei Y-Dir Body Ef EV Y-Dir X-Dir 𝜑s < 0 Large barrier for electrons to diffuse 22
Slide 23: Depletion
Gate Depletion VGS > 0V, VDS = 0V Source Drain Metal Oxide X-Dir N+ N+ P-sub q𝝋s ECC E q𝝋s Eii Y-Dir E Body Eff E EVV E Y-Dir X-Dir 𝜑s > 0 Large barrier for electrons to diffuse 23
Slide 24: Inversion
Gate Inversion VGS > VT, VDS = 0V Source Drain Metal Oxide X-Dir N+ N+ P-sub EC q𝝋s q𝝋s Y-Dir Ei Body Ef EV Inversion (onset of strong inversion) Y-Dir X-Dir 𝜑s = 2∅𝑏 Barrier is reduced, no net current as potential drop along the channel is zero 24
Slide 25: Inversion + VDS ↑
Gate Inversion + VDS ↑ VGS > VT, VDS = 0V Source Drain Metal Oxide X-Dir N+ N+ P-sub EC q𝝋s q𝝋s Y-Dir Ei Body Ef EV Inversion (onset of strong inversion) Y-Dir X-Dir 𝜑s = 2∅𝑏 Thermionic injection at source (diffusion) over potential barrier and then drift towards at the drain edge 25
Slide 26: Pinch Off
Gate Pinch Off VGS > VT, VDS = VGS - VT Source Drain Metal Oxide X-Dir N+ N+ P-sub EC q𝝋s Y-Dir Ei Body Ef EV Inversion (onset of strong inversion) Y-Dir X-Dir 𝜑s = 2∅𝑏 Channel is pinched off, large electric field at drain side swept the electrons to drain 26
Slide 27: Saturation
Gate Saturation VGS > VT, VDS > VGS - VT Source Drain Metal Oxide X-Dir N+ N+ P-sub EC q 𝝋s Y-Dir Ei Body Ef EV Inversion (onset of strong inversion) Y-Dir 𝝋s = 2∅𝒃 Channel formation further reduces, channel current does not increase further, reaches saturation 27
Slide 28: MOSFET Non-Ideal Effects
MOSFET Non-Ideal Effects 28
Slide 29: MOSFET Non-Ideal Effects
MOSFET Non-Ideal Effects 1. Subthreshold Leakage 2. Drain Induced Barrier Lowering (DIBL) 3. Gate Induced Drain Leakage (GIDL) 29
Slide 30: ID-VG Characteristics: Linear vs Log Scale
ID-VG Characteristics Linear vs Log Scale 𝐼𝐷𝑆 log 𝐼𝐷𝑆 𝑒 (𝑉𝐺−𝑉𝑇 )/𝑚𝑘𝐵 𝑇 Exponential dependence 𝑉𝑇 𝑉𝐺𝑆 𝑉𝑇 𝑉𝐺𝑆 ▪ It appears the subthreshold region is linear in log scale [i.e: ln ex = x] ▪ This implies, subthreshold conduction (leakage) before 𝑉𝑇 (threshold) is exponential…
Slide 31: Subthreshold Conduction
Subthreshold Conduction Subthreshold Slope/Swing (SS) • SS: The gate voltage required to increase or reduce IDS by one decade Drain Current (Log scale), 𝐼𝐷𝑆 • SS is given by the inverse of the slope of log IDS vs VGS 𝑑𝑙𝑜𝑔 𝐼𝐷𝑆 -1 Threshold SS = [ ] [unit: mv/dec] 𝑑𝑉𝐺𝑆 • Note that SS >…
Slide 32: Carrier Distribution
Carrier Distribution DoS, g(E) Fermi function, f(E) Carrier Concentration, n(E)dE = g(E)f(E)dE E Exponential tail of electron distribution Electron distribution Ec Ec Fermi Level Midgap x Ef = Ef EV EV Hole distribution 𝟏 𝒇 𝑬 = (𝑬−𝑬𝒇 ) ൗ 𝟏+𝒆 𝒌𝑻 32
Slide 33: MOSFET Operation [OFF State]
MOSFET Operation [OFF State] OFF is not completely OFF! Metal Oxide Exponential tail of S D electron distribution P-sub Higher E Thermal diffusion of carrier injection mechanism n(E) 𝐥𝐨𝐠 𝑰𝑫𝑺 Ec Ev 33
Slide 34: MOSFET Operation [OFF State → Increasing VGS]
MOSFET Operation [OFF State → Increasing VGS] Why subthreshold slope is linear in log scale? (Exponential in linear scale) Consider a hypothetical scenario, a minor increase in the gate Metal voltage (within the subthreshold region) can lead to: Oxide Exponential tail of S D • Revealing exponentiall
Slide 35: Carrier Distribution [Low T vs High T]
Carrier Distribution [Low T vs High T ] Density of states, g(E) Fermi function, f(E) Carrier Concentration, n(E) = g(E)f(E) E Exponential tail of electron distribution High T Electron distribution Ec Fermi Level Midgap x Ef = Ef EV Hole distribution 𝟏 Higher temperature results in larger amount of…
Slide 36: Subthreshold Leakage: Poor vs Good Subthreshold Slope
Subthreshold Leakage Poor vs Good Subthreshold Slope Drain Current (Log scale), 𝐼𝐷𝑆 • Device B exhibits a poorer (larger) subthreshold slope (SS) compared to device A, despite having matched VT • Smaller SS (steeper slope) is necessary to minimize the A OFF-state leakage • Question: What methods…
Slide 37: Subthreshold Leakage
Metal Subthreshold Leakage N+ Oxide N+ P-sub dVG 𝑑𝜑𝑠 𝐶𝑜𝑥 1 = = Cox 𝑑𝑉𝐺𝑆 𝐶𝑜𝑥+𝐶𝑑𝑒𝑝 𝑛 𝐶𝑑𝑒𝑝 𝑞𝜑𝑠 𝑛 =1+ 𝑑𝜓𝑠 𝑑𝑉𝐺𝑆 𝐶𝑜𝑥 Ef Ef 𝑑𝜑𝑠 = Cdep 𝑛 𝑉𝐺𝑆 𝜑𝑠 = 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡 + 𝑛 𝑉 𝑞𝜑𝑠 𝑞[𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡+ 𝐺𝑆 𝑛 ] 𝑞𝑉𝐺𝑆 log 𝐼𝐷𝑆 𝐼𝐷𝑆 ∝ 𝑛𝑠 ∝ 𝑒𝑥𝑝 ∝ 𝑒𝑥𝑝…
Slide 38: Subthreshold Conduction [Lowering VT]
Subthreshold Conduction [Lowering VT] Why it matters, what is the issue with non-scalability of SS? Drain Current (Log scale), 𝐼𝐷𝑆 60mV • Both Device A & B have similar SS (i.e: 60mV/decade) B • However, device B shows 10x increase in leakage for 60mV VT reduction A • Non-scalability of SS…
Slide 39: Drain Induced Barrier Lowering [DIBL]
Drain Induced Barrier Lowering [DIBL] Metal • Field encroachment from the drain reduces the Oxide electron injection barrier at the source, leading to VT S Lg D lowering that is influenced by: • Shorter channel (gate) length (Lg) Barrier Lowering L4 < L3 L3 < L2 L2 < L1 • Elevated VDS • Gate is losi
Slide 40: DIBL [VDS Impact]
DIBL [VDS Impact] • DIBL reduces VT at elevated VDS levels Drain Current (Log scale), 𝐼𝐷𝑆 • DIBL Coefficient = Delta VT/Delta VDS • Unit: mV/V • Quantifies VT lowering per unit increase in Poor SS High VDS VDS, ideal case is zero Low VDS • DIBL degrades SS (larger) VT VT Gate-Source Voltage, VGS…
Slide 41: DIBL [VDS Impact and Short vs Long Channel]
DIBL [VDS Impact and Short vs Long Channel] Short Channel Effect (SCE) • Short channel will have larger drain electric field Drain Current (Log scale), 𝐼𝐷𝑆 Short Channel penetration towards source Long Channel • Short channel shows larger DIBL shift High VDS Low VDS Gate-Source Voltage, VGS 41
Slide 42: Thin Body Channel ➔ Improves DIBL
Thin Body Channel ➔ Improves DIBL Metal Oxide S D • The penetration of the electric field toward the source decreases (due to bulk encroachment) when using a thinner body Electric field encroachment from drain through bulk (more flux/fringing field interaction) • Additional strategies to improve DIB
Slide 43: Gate Induced Drain Leakage (GIDL)
Gate Induced Drain Leakage (GIDL) • GIDL typically occurs when the gate is biased to VG < 0 log 𝐼𝐷𝑆 𝑉𝐷𝑆 =1.1V accumulation and the drain is ramped to reverse 𝑉𝐷𝑆 =0.05V voltages D VD >0 • The device is driven to deep depletion at gate- Metal 𝑒 (𝑉𝐺𝑆 −𝑉𝑇 )/𝑚𝑘𝐵 𝑇 Oxide drain (N+)…
Slide 44: Closing Thoughts
Closing Thoughts MOSFET scaling over the years • MOSFET is the heart of semiconductor industry 20µm 10µm 6µm • Powerful and efficient semiconductor 3µm 1.5µm devices/increasing computing power is enabled 1µm 0.8µm 0.6µm 0.35µm by exponential increase in MOSFET counts 0.25µm 0.18µm 0.13µm 90nm 65nm •
Slide 45: Glossary
Glossary 45
Slide 46: Glossary
Glossary Term or acronym Definition/description Accumulation A condition in MOSCAP where the majority carriers accumulate at the surface due to the applied gate potential Body Bulk crystal or polycrystalline silicon region where the majority carriers accumulate, deplete or invert depending on the ap
Slide 47: Glossary
Glossary Term or acronym Definition/description MOSCAP Metal Oxide Semiconductor Capacitor. It is a two-terminal device used to understand the fundamentals of MOSFET operation MOSFET Metal Oxide Semiconductor Field Effect Transistor. It is a four-terminal device used in both digital and analog appli
Slide 48: References
References 48
Slide 49: Reference
Reference 1. Fundamental of Modern VLSI Devices, Yuan Taur and Tak H. Ning 2. Modern Semiconductor Devices for Integrated Circuits, Chenming Hu 3. Semiconductor Fundamentals, Robert F. Pierret 4. Semiconductor Physics and Devices, Donald Neamen 5. Physics of Semiconductor Devices, Simon Sze 49
Slide 50: © 2022–2025 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject
© 2022–2025 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Statements regarding products, including statements regarding product features,