Infineon Technologies Ag · XETR:IFX

Infineon Technologies — Technical Presentation (March 2015)

77 slides from Infineon Technologies's technical presentation, Mar 16, 2015

1. Slide 1: Practical Application of 600 V GaN HEMTs in Power Electronics

   Professional Education Seminar S17 Practical Application of 600 V GaN HEMTs in Power Electronics Monday March 16, 2015 8:30 – 12:00 Eric Persson, GaN Applications

2. Slide 2: Seminar Outline

   Seminar Outline  Limitations of today‟s 600 V Silicon  Topologies where superjunction performs well  Topologies where superjunction application is limited  GaN HEMT characteristics – Depletion-mode, cascode, enhancement-mode – GaN applied to hard and soft-switching topologies  Gate drive consid

3. Slide 3: What needs improvement?

   What needs improvement? For same Rds(on), improve all the charge parameters:  Reduce Coss nonlinearity – Nonlinearity makes timing and dv/dt control challenging  Reduce Qoss (and therefore Eoss) magnitude  Reduce Coss dissipation factor  Improve body diode dynamic performance – Reduce/eliminate

4. Slide 4: Topologies where superjunction works well

   Topologies where superjunction works well  Unipolar current flow, hard or soft-switched  Two-transistor forward – Hard switched, partial valley switched  Boost PFC – CCM or CrCM  Flyback – Hard switched, partial valley switched  Why? – Superjunction has low Rds(on)*Eoss figure of merit – Body d

5. Slide 5: 2-Transistor Forward Converter (2TF)

   2-Transistor Forward Converter (2TF) Vin APEC 2015 Seminar S17 5

6. Slide 6: 2TF voltage and current waveforms

   2TF voltage and current waveforms Ref: Thierry Sutto, “2 switch forward current mode converter,” ON semi app note AND8373/D APEC 2015 Seminar S17 6

7. Slide 7: 2TF FET turn-on loss measurement

   2TF FET turn-on loss measurement Ref: Thierry Sutto, “2 switch forward current mode converter,” ON semi app note AND8373/D APEC 2015 Seminar S17 7

8. Slide 8: 2TF FET turn-on loss analysis

   2TF FET turn-on loss analysis  This accounts for the “crossover” loss – Where the transistor is supporting simultaneous V and I  What is missing?  This suggests that if Δt goes to 0, Turn-on loss = 0 Ref: Thierry Sutto, “2 switch forward current mode converter,” ON semi app note AND8373/D APEC 20

9. Slide 9: What about the Eoss of the FET itself?

   What about the Eoss of the FET itself? Vd Vd Simplified SiC v DS t  Schottky Schematic Io i D t  iD  Note: This is not Qrr iG vDS  Vd 0 t DF Cak IO PLOSSt  C gd1 RG  C ds VGG C gs  Current Commutation Qsw Discharge Equivalent Circuit APEC 2015 Seminar S17 9

10. Slide 10: 2TF FET turn-off loss

    2TF FET turn-off loss  Turn-off losses limited entirely by gate drive – If you can turn-off the gate extremely fast, get ZVS Ref: Thierry Sutto, “2 switch forward current mode converter,” ON semi app note AND8373/D APEC 2015 Seminar S17 10

11. Slide 11: 2 Transistor Forward Summary

    2 Transistor Forward Summary  This is a unipolar topology – Superjunction already works well – Body diode performance is unimportant  Switch losses are dominated by: – Conduction – Turn-on speed – Eoss – Turn-off speed  Possible switch improvements – For a given Rds(on): – Reduced Eoss (stored en

12. Slide 12: Flyback Converter

    Flyback Converter  Avalanche risk Vin IL Vds Vgs APEC 2015 Seminar S17 12

13. Slide 13: Flyback turn-on timing is critical

    Flyback turn-on timing is critical  Eoss dissipated proportional to Vds2  Strong dependence on timing turn-on to waveform – Turning on at peak versus valley – big difference in Eoss Vds Vds Iin Iin Vgs Vgs APEC 2015 Seminar S17 13

14. Slide 14: Flyback Summary

    Flyback Summary  This is a unipolar topology – Superjunction already works well – Body diode performance is unimportant – Avalanche or overvoltage capability likely necessary  Switch losses are dominated by: – Conduction – Turn-on speed – Eoss (valley switching can minimize loss) – Turn-off speed

15. Slide 15: Standard boost PFC

    Standard boost PFC  SB typically superjunction  DB SiC Schottky for lowest loss  Can achieve >96% efficiency REF: L. Huber, Y. Jang, M. Jovanovic, “Performance Evaluation of Bridgeless PFC Boost Rectifiers,” IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 3, MAY 2008 APEC 2015 Seminar S17 15

16. Slide 16: Standard boost PFC

    Standard boost PFC  Typical operating frequency <70 kHz – Keep fundamental and 2nd harmonic below 150 kHz EMI – Increasing frequency increases switching loss  Control mode typically Continuous Conduction Mode – CCM balances ripple current losses and switching loss  Can be operated Discontinuous o

17. Slide 17: Standard boost PFC summary

    Standard boost PFC summary  This is a unipolar topology – Superjunction already works well – Body diode performance is unimportant  Switch losses are dominated by: – Conduction (especially severe for high ripple CrCM and DCM) – Turn-on speed – Eoss (only for CCM) – Turn-off speed  Possible switch

18. Slide 18: What about bridgeless PFC topologies?

    What about bridgeless PFC topologies?  Dual boost – semi bridgeless  S1 S2 commonly superjunction, D1 D2 SiC Ref: A. F. Souza and I. Barbi, “High power factor rectifier with reduced conduction and commutation losses,” in Proc. Int. Telecommunication Energy Conf., Jun. 1999, pp. 8.1.1–8.1.5. APEC 2

19. Slide 19: Dual boost PFC summary

    Dual boost PFC summary  This is a unipolar topology – Superjunction already works well – Body diode performance is unimportant  Switch losses are dominated by: – Conduction (especially severe for high ripple CrCM and DCM) – Turn-on speed – Eoss (only for CCM) – Turn-off speed  Possible switch imp

20. Slide 20: Why not totem-pole PFC with superjunction?

    Why not totem-pole PFC with superjunction?  Hard-switched half-bridge requires good body-diode REF: J. C. Salmon, “Circuit topologies for PWM boost rectifiers operated from 1-phase and 3-phase ac supplies and using either single or split dc rail voltage outputs,” APEC, Mar. 1995, pp. 473–479. APEC

21. Slide 21: Hard-switched half-bridge

    Hard-switched half-bridge VSW = VDS(Q2) IL Q1 IQ2 IL 0 t VSW IQ1 This is Q1 Eoss. Q2 Eoss discharge Q2 current is internal, not seen externally P(t)Q2 Turn-on Reverse EOSS Loss Recovery Loss Loss APEC 2015 Seminar S17 21

22. Slide 22: Summary: topologies with limited superjunction use

    Summary: topologies with limited superjunction use  Bipolar current flow topologies – Anywhere diode recovery is important  Half-bridge hard-switching – Totem-pole bridgeless boost CCM (except line polarity switch) – Inverters, motor drives  Half-bridge soft-switching or resonant? Depends… – Limi

23. Slide 23: GaN High Electron Mobility Transistor (HEMT)

    GaN High Electron Mobility Transistor (HEMT)  Depletion-mode basic HEMT – Normally-on is a problem for power electronics  2 methods to achieve normally-off – Cascode – Enhancement-mode  GaN cascode characteristics  GaN enhancement-mode characteristics  GaN application summary – Hard-switching –

24. Slide 24: GaN High Electron Mobility Transistor (HEMT)

    GaN High Electron Mobility Transistor (HEMT)  Depletion-mode (normally-on) HEMT  Si substrate for low cost  Normally-on potential problem for power electronics Ref: Jones, E.A.; Wang, F.; Ozpineci, B., "Application-based review of GaN HFETs," Wide Bandgap Power Devices and Applications (WiPDA) 20

25. Slide 25: Depletion-mode HEMT

    Depletion-mode HEMT  Normally-on – Essentially a resistor that can be turned-off with -gate bias – Potential issues with power-up and power-down – Requires additional master enable switch – Requires negative gate drive  Low area specific on-resistance  Bi-directional conduction – No intrinsic bod

26. Slide 26: Cascode Provides Normally-OFF Function

    Cascode Provides Normally-OFF Function  Native d-mode GaN HEMT + LV Si FET in cascode – Rds(on) is compromised to shift threshold positive  Cascode has easy gate drive  Cascode includes excellent body diode  2-chip solution no more difficult than IGBT  Almost zero “Miller Effect” D – C dv/dt im

27. Slide 27: Cascode Conduction Modes

    Cascode Conduction Modes Ref: Xiucheng Huang, Fred C. Lee, Qiang Li, “Characterization and Enhancement of 600V Cascode GaN Device,” CPES PMC Review, March 11, 2015 APEC 2015 Seminar S17 27

28. Slide 28: Body diode reverse-recovery

    Body diode reverse-recovery  >100x lower Qrr for GaN cascode GaN cascode switch 10 A/div Superjunction APEC 2015 Seminar S17 28

29. Slide 29: Comparing GaN cascode to superjunction

    Comparing GaN cascode to superjunction  1st Generation GaN cascode Parameter GaN cascode Equivalent SJ Package 6x8 mm PQFN 8x8 mm PQFN GaN 25% smaller package Vdss 600 V 650 V Rdson typ 25°C 135 mΩ 115 mΩ Rdson typ 125°C 225 mΩ 230 mΩ GaN 1.67x; SJ 2x Qg (10V Vgs, 480V Vds) 8.8 nC 35 nC GaN ~4X low

30. Slide 30: Turn-on waveform, 135 mΩ (typ) cascode

    Turn-on waveform, 135 mΩ (typ) cascode  Hard-switching Rg = 2Ω. ~9 µJ EON Vds 100 V/div 5 A/div Vgs 10 V/div APEC 2015 Seminar S17 30

31. Slide 31: GaN HEMT Safe Operating Area

    GaN HEMT Safe Operating Area  Measured destruct current >2x higher than calculated thermal limit 100 μs 10 Drain Current, ID (A) 1 ms 10 ms 1 Experimental data from 190 mΩ max cascode prototype 0.1 100 Drain-Source Voltage, VDS (V)  Lines represent calculated thermal limit – points are measured fa

32. Slide 32: GaN performance interdependent on package

    GaN performance interdependent on package  Two key factors for minimizing losses: – Minimize GaN – Si interconnect inductance – Eliminate common-source inductance with Kelvin connection REF: Z. Liu, X. Huang, FC Lee, Q. Li, “Investigation of Package Influence on High Voltage Cascode GaN HEMT with S

33. Slide 33: Die-on-die cascode construction

    Die-on-die cascode construction  Minimizes parasitic impedance between HEMT and FET – Faster switching transitions, less ringing and overshoot D LV Si MOSFET mounted on Depletion-Mode Source pad of GaN on Si die GaN HEMT Low Voltage Si MOSFET G S GaN on Si US Pat. No. 8,847,408 HEMT die APEC 2015 S

34. Slide 34: E-mode GaN HEMT Structures

    E-mode GaN HEMT Structures a) P-gate enhancement-mode b) P-gate enhancement-mode (gate injection) Ref: Jones, E.A.; Wang, F.; Ozpineci, B., "Application-based review of GaN HFETs," Wide Bandgap Power Devices and Applications (WiPDA) 2014, pp.24-29, 13-15 Oct. 2014 APEC 2015 Seminar S17 34

35. Slide 35: Enhancement-Mode HEMT (Gate Injection)

    Enhancement-Mode HEMT (Gate Injection) off Ref: http://www.semicon.panasonic.co.jp/en/news/contents/2013/apec/panel/APEC2013_GaN_FPD_WEB.pdf APEC 2015 Seminar S17 35

36. Slide 36: Gate Characteristics (Enhancement Mode)

    Gate Characteristics (Enhancement Mode)  Typical non-insulated gate characteristic – Gate injection uses small DC current (e.g. 10 mA) Ref: Jones, E.A.; Wang, F.; Ozpineci, B., "Application-based review of GaN HFETs," Wide Bandgap Power Devices and Applications (WiPDA) 2014, pp.24-29, 13-15 Oct. 20

37. Slide 37: Output Characteristics (Enhancement Mode)

    Output Characteristics (Enhancement Mode)  HEMT turns back ON when drain goes below G, S Ref: Jones, E.A.; Wang, F.; Ozpineci, B., "Application-based review of GaN HFETs," Wide Bandgap Power Devices and Applications (WiPDA) 2014, pp.24-29, 13-15 Oct. 2014 APEC 2015 Seminar S17 37

38. Slide 38: Reverse Bias Diode-Like Behavior

    Reverse Bias Diode-Like Behavior + Vg1 - Equivalent Circuit when Vg = 0 VGS’ = VD’S’ D D D’ G G G + S S S’ Vg2 - S’ = drain acting as source in reverse bias D’ = source acting as drain in reverse bias APEC 2015 Seminar S17 38

39. Slide 39: Forward and Reverse I-V Characteristics

    Forward and Reverse I-V Characteristics  HEMT eventually saturates at very high current Ref: http://www.semicon.panasonic.co.jp/en/news/contents/2013/apec/panel/APEC2013_GaN_FPD_WEB.pdf APEC 2015 Seminar S17 39

40. Slide 40: GaN, superjunction, (& SiC) transfer curves

    GaN, superjunction, (& SiC) transfer curves  Cascode superjunction and SiC ~135 mΩ typical  E-mode GaN (non GIT) ~50mΩ (135 mΩ @ 150°C) Transfer curve E-mode GaN Cascode GaN SiC 10 SJ 1 ID (A) 0.1 0.01 0 2 4 (V) VGS 6 8 10 APEC 2015 Seminar S17 40

41. Slide 41: Comparing GaN vs SJ Qoss

    Comparing GaN vs SJ Qoss REF: M. Treu, E. Vecino, M. Pippan, O. Häberlen, G. Curatola, G. Deboy, M. Kutschak, U. Kirchner,” The role of silicon, silicon carbide and gallium nitride in power electronics,” IEEE International Electron Devices Meeting, December, 2012 APEC 2015 Seminar S17 41

42. Slide 42: Comparing Coss, Qoss, Eoss GaN vs SJ

    Comparing Coss, Qoss, Eoss GaN vs SJ Blue = superjunction Red = e-mode HEMT Both ~70 mΩ max Rds(on) APEC 2015 Seminar S17 42

43. Slide 43: Comparing GaN vs superjunction turn-off

    Comparing GaN vs superjunction turn-off  LLC topology looking at low-side switch – 400 V bus, 2 A – Same Rds(on) Superjunction Cascode GaN Vds Vds Vgs Vgs Id Id APEC 2015 Seminar S17 43

44. Slide 44: Avalanche and overvoltage

    Avalanche and overvoltage  Superjunction has junction with avalanche capability – Useful in circuits with unclamped inductive energy (flyback)  GaN has no junction, no avalanche behavior – GaN ultimately breaks down destructively at ~2x rating – Overvoltage spikes are allowed depending on supplier

45. Slide 45: GaN Device Summary

    GaN Device Summary  Both cascode and enhancement mode – compared to superjunction:  Provides MUCH lower Qrr (zero for e-mode) – Enables use of efficient half-bridge topologies  Provide smaller, more linear Qoss – Reduces deadtime in resonant and ZVS circuits  Provide lower gate charge Qg – Lower

46. Slide 46: Applications of GaN

    Applications of GaN APEC 2015 Seminar S17 46

47. Slide 47: Gate Drive

    Gate Drive  Cascode – standard Si gate drivers work – Vgs(th) is potential issue – Common Source Inductance is a concern as always – C dv/dt induced gate currents – Kelvin gate-source connections – Advantages of floating gate drive APEC 2015 Seminar S17 47

48. Slide 48: Gate drive challenges for low threshold devices

    Gate drive challenges for low threshold devices DC Bus DC Bus L L Isolated Isolated ?  Common Source Inductance distorts Vgs  Kelvin source connection eliminates CSI  …BUT can cause system grounding problems for driver APEC 2015 Seminar S17 48

49. Slide 49: Isolated gate drive + Kelvin source connection

    Isolated gate drive + Kelvin source connection DC Bus DC Bus L L Isolated Isolated ?  Isolating both high and low-side drivers solves system ground bounce issues which can affect current sense and logic ground APEC 2015 Seminar S17 49

50. Slide 50: Gate drive for gate injection

    Gate drive for gate injection REF: T. Morita, H. Hanada, S Ujita, M Ishida, T. Ueda, “99.3% Efficiency Boost-up Converter for Totem-pole Bridgeless PFC Using GaN Gate Injection Transistors,” Proc. PCIM Europe, 20-22 May 2014 APEC 2015 Seminar S17 50

51. Slide 51: Gate drive summary

    Gate drive summary  Cascode GaN: – Standard FET gate driver compatibility – Lower Qg for given current-handling capability – ZVS turn-off easier to achieve  Enhancement-mode GaN – Low threshold, noise sensitivity, negative drive can help – Tighter limits on Vgs – Very low Qg – Kelvin source connec

52. Slide 52: Totem-Pole PFC Full-Bridge

    Totem-Pole PFC Full-Bridge 60Hz High Frequency Polarity Half-Bridge Switch This half-bridge This half-bridge is GaN cascode Q1 Q3 is superjunction DC Bus EMI AC Filter Q2 Q4 LINE APEC 2015 Seminar S17 53

53. Slide 53: Totem-Pole PFC Full-Bridge

    Totem-Pole PFC Full-Bridge  2.5 kW all SMD power stage proof-of-concept  GaN boost stage 70 mΩ max enhancement-mode  superjunction sync line rectifiers Bottom View of PCB Q1 Superjunction Q3 GaN Superjunction GaN EMI Filter Q2 Q4 APEC 2015 Seminar S17 54

54. Slide 54: Totem-Pole PFC Full-Bridge

    Totem-Pole PFC Full-Bridge  Input 230 VAC  Output 400 VDC, 6.25 A  CCM 45 to 65 kHz PFC Inductor Output EMI filter + Bus Capacitors FAN Heatsink Output Input Input EMI filter Aux power supply Control board APEC 2015 Seminar S17 55

55. Slide 55: Totem-Pole PFC full-bridge performance

    Totem-Pole PFC full-bridge performance  >99% efficiency from 18-70% load Measured Efficiency - PFC, VIN=230VAC 99.4 99.2 99.0 Efficiency (%) 98.8 98.6  45kHz  65kHz 98.4 98.2 0 500 1000 1500 2000 2500 3000 POUT (W) Complete Power Stage. Vin=230 V, Tamb=25° C APEC 2015 Seminar S17 56

56. Slide 56: Totem Pole PFC

    Totem Pole PFC  No diode drops – only switch conduction voltage  Very high efficiency possible >99%  Lower component count than other bridgeless topologies  Topology is enabled by GaN HEMT – Traditional Si FETs have too much body-diode Qrr Large recovery currents and high losses  Topology is In

57. Slide 57: Totem Pole PFC Future

    Totem Pole PFC Future  MHz ZVS – still achieving 99% efficiency  Multiphase architectures to minimize ripple  Digital control to optimize performance & efficiency Ref: Zhengyang Liu, Fred C. Lee, QiangLi, “Digital Control for MHz Totem-pole PFC Rectifier,” CPES PMC Review, Mar.11, 2015 APEC 2015

58. Slide 58: LLC Resonant DC-DC

    LLC Resonant DC-DC  Popular topology today using superjunction  Frequency range <200 kHz typically  Caution required to prevent hard-switching APEC 2015 Seminar S17 59

59. Slide 59: LLC typical waveforms and circuit

    LLC typical waveforms and circuit APEC 2015 Seminar S17 60

60. Slide 60: GaN enables shorter deadtime vs SJ @ 1MHz

    GaN enables shorter deadtime vs SJ @ 1MHz  Shorter deadtime lowers rms current I2 Primary I2 Secondary Gate Drive GaN 3.84A2 48.0A2 0.24W Superjunction 4.93A2 64.6A2 1.88W Difference +28.3% +34.6% +685% 80ns dead time GaN SJ FET 200ns dead time Vds icentertap iprim Vgs APEC 2015 Seminar S17 61

61. Slide 61: Nonlinear Qoss Charge Affects Deadtime

    Nonlinear Qoss Charge Affects Deadtime 500 450 3.3X longer charge-up time 400 350 300 Volts 250 200 150 Qoss Measurement Circuit 100 50 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Time (µs) APEC 2015 Seminar S17 62

62. Slide 62: Cascode Charge Balance During ZVS Turn-ON

    Cascode Charge Balance During ZVS Turn-ON Improper charge balance Properly balanced Cascode results in loss of ZVS achieves full ZVS  Significant energy loss  No energy loss IL Vsw VDS-Si Measured Results: IR-Infineon Cascode X. Huang, W. Du, Z. Liu, F. C. Lee, and Q. Li, “Performance Analysis of

63. Slide 63: Cascode Charge Balance During ZVS Turn-OFF

    Cascode Charge Balance During ZVS Turn-OFF Improper charge balance Properly balanced Cascode results in Si avalanche no avalanche, full ZVS  Significant energy loss  No energy loss Avalanche Vsw VDS-Si IL Measured Results: IR-Infineon Cascode X. Huang, W. Du, Z. Liu, F. C. Lee, and Q. Li, “Perform

64. Slide 64: ZVS phase-shifted full-bridge

    ZVS phase-shifted full-bridge  ZVS over most of power range except light-load  Current-doubler output effective for 12 V and below APEC 2015 Seminar S17 65

65. Slide 65: ZVS phase-shifted full-bridge

    ZVS phase-shifted full-bridge  1 kW 380 V to 12 V  350 kHz  120 W/in3 APEC 2015 Seminar S17 66

66. Slide 66: ZVS phase-shifted full-bridge

    ZVS phase-shifted full-bridge  Waveforms at 50% load APEC 2015 Seminar S17 67

67. Slide 67: ZVS phase-shifted full-bridge efficiency

    ZVS phase-shifted full-bridge efficiency Efficiency vs Percentage Load 97 96 380V to 12V 95 fsw = 350 kHz 94 Load Efficiemcy 93 10% 89.5% 92 20% 94% 40% 96.1% 91 50% 96.4% 90 80% 96.3% 100% 95.7% 89 0 10 20 30 40 50 60 70 80 90 100 LOAD in % (1000W max) APEC 2015 Seminar S17 68

68. Slide 68: Efficiency vs Frequency at half-load

    Efficiency vs Frequency at half-load  Comparing GaN cascode vs superjunction Freq Efficiency_GaN Efficiemcy_SJ [Khz] [%] [%] 97 100 96.7 96.5 200 96.5 96.2 96.5 300 96.4 95.4 350 96.3 95 96 400 95.9 94 450 95.6 95.5 500 95.4 Efficiency GaN efficiency 95 SJ efficiency 94.5 94 93.5 0 100 200 300 400

69. Slide 69: Why GaN for Motor Drive Applications?

    Why GaN for Motor Drive Applications?  Switching speed is not necessarily a key issue for drives:  Typically want dv/dt <6V/ns (GaN can switch >10x faster) – I=C dv/dt currents in motor windings can result in failures – Corona and partial-discharge creates ozone and erodes insulation – Common-mode

70. Slide 70: Typical Compressor Drive Today

    Typical Compressor Drive Today BIAS LINE EMI CONTROL & AC POWER GATE INPUT FILTER PWM MOTOR SUPPLY DRIVERS INPUT DC BUS OUTPUT INVERTER RECTIFIER CAP APEC 2015 Seminar S17 71

71. Slide 71: Conduction Voltage for Same Footprint Size

    Conduction Voltage for Same Footprint Size Comparing Conduction voltage of IGBT vs FET (measured data) 3.0 2.5 2.0 1.5 Vds or Vce (Volts) 1.0 0.5 0.0 IRGR4045D -0.5 0.8Ω Si 0.16Ω GaN -1.0 -1.5 -2.0 -2.5 -3.0 -5 -4 -3 -2 -1 0 1 2 3 4 5 Drain or Collector current (Amps) APEC 2015 Seminar S17 72

72. Slide 72: Total Power Loss Summary (per switch)

    Total Power Loss Summary (per switch) 1.60 1.40 1.20 Watts loss @ Iout = 1A rms 1.00 conduction 0.80 turn-off turn-on Fixed 0.60 0.40 0.20 0.00 Si FET IGBT GaN cascode APEC 2015 Seminar S17 73

73. Slide 73: Cascode GaN dv/dt control via Gate Modulation

    Cascode GaN dv/dt control via Gate Modulation 2A Turn off 2A Turn on 50ns/div 100ns/div Vsw Vgs Vgs 3.7V/ns 3.3V/ns Vsw  Dv/dt control possible by modulating cascode gate-drive current  This places HEMT in linear region increasing switching times and losses  Unknown if this affects long-term reli

74. Slide 74: GaN HEMT Short-Circuit Capability

    GaN HEMT Short-Circuit Capability  Initial devices are high-gain – limited SCSOA – Typically ~ 1 µs @ 300V  Likely tradeoff between gain and SCSOA similar to IGBTs Ref: Xing Huang; Dong Young Lee; Bondarenko, V.; Baker, A.; Sheridan, D.C.; Huang, A.Q.; Baliga, B.J., "Experimental study of 650V AlG

75. Slide 75: Summary

    Summary  GaN HEMTs offer performance improvements for power electronic applications – Benefits are strongly topology-dependent – Just dropping GaN into existing circuit may show little benefit  Half-bridge topology is good match for GaN – Half-bridge requires good dynamic reverse conduction – Both

76. Slide 76: Questions?

    I¢R Questions?

77. Slide 77: References

    References 1) Alex Lidow, Johan Strydom, Michael de Rooij, David Reusch, “GaN Transistors for Efficient Power Conversion, 2nd Edition,” Wiley, ISBN: 978-1-118-84476-2, Sept. 2014 2) Fedison, J.B.; Fornage, M.; Harrison, M.J.; Zimmanck, D.R., "Coss related energy loss in power MOSFETs used in zero-vo

Infineon Technologies — Technical Presentation (March 2015) on 6ix