Atomera Incorporated · NASDAQ:ATOM
Atomera — Investor Presentation (November 2025)
41 slides from Atomera's investor presentation, November 2025
Slide 1: Investor Presentation
Investor Presentation November 2025 Atomera Incorporated 1
Slide 2: Safe Harbor
Safe Harbor This presentation contains forward-looking statements concerning Atomera Incorporated (““Atomera,” the “Company,” “we,” “us,” and “our”). The words “believe,” “may,” “will,” “potentially,” “estimate,” “continue,” “anticipate,” “intend,” “could,” “would,” “project,” “plan,” “expect” and s
Slide 3: Mears Silicon Technology (MST®)
Mears Silicon Transistor enhancement Technology technology for the High Leverage IP Licensing Business (MST®) $600B semiconductor market Model Quantum Engineered Materials Top Tier Strong, Growing and Management Team Defensible Patent Portfolio 3
Slide 4: MST Technology
MST Technology Potential Benefits ► Improved Efficiency ▪ Higher transistor performance ▪ Lower power consumption ▪ Better reliability ► Lower cost ▪ Reduced die size ▪ Improved yield ▪ Higher throughput ► Same benefits as a node shrink Atomera Incorporated 4
Slide 5: Strong and Growing IP Portfolio
Strong and Growing IP Portfolio Discoverable 402 Patents Issued and Pending These distinctive layers are visible on products using MST 114 US Patents 167 100 67 Pending Foreign US 121 Foreign Patents Core MST Method and Device Extensive know-how MST Enabled Devices/Architecture Extends life and valu
Slide 6: Target Customers & Partners
Target Customers & Partners Integrated Device Manufacturers Foundry Fabless Tool Suppliers (Partners) Atomera Incorporated 6
Slide 7: Customer Status
Customer Status v Customer Wafer Manufacturing Atomera MST® Deposition Customer MST® Deposition Phase 1. Planning 2. Setup 3. Integration 4. Installation 5. Qualification 6. Production Engagement Phases 2 • 20 customers, 26 engagements 10 • Working with more than half of the world’s top semiconducto
Slide 8: Customer Engagement & Revenue Model
Customer Engagement & Revenue Model v Customer Wafer Manufacturing Atomera MST® Deposition Customer MST® Deposition 1. Planning 2. Setup 3. Integration 4. Installation 5. Qualification 6. Production Phase Engineering Service • MST deposition on customer wafers Fees • Integration consulting • R&D lic
Slide 9: Productization cycle
Productization cycle Phase 5 Phase 6 Process development with TCAD Freeze PDK Process Volume (Process Design Kit) Production Wafers Qualification MST Silicon manufactured Installation Validation with MST Phase 4 Chip ChipDesigns Designs Chip Designs Start Chip Designs Start Start Atomera Incorporate
Slide 10: Revenue potential and timing
Revenue potential and timing Easier integration, faster time to revenue MST starting wafers • RFSOI, GaN, Next Gen DRAM, etc High volume potential Longer integration, higher revenue potential products • GAA Logic, DRAM, Power, Flash memory, etc. Breakthrough, enabling New disruptive technologies mat
Slide 11: MST Key Benefits Across Nodes
MST Key Benefits Across Nodes Leading Analog & Mainstream FinFET GAA RF SOI Planar Mobility 8% 20% 25% 10% 15+% Dopant Engineering 20% 15% 15% 15% 20% Reliability (TDDB/BTI) 25% 25% 25% 25% 180nm 130nm 90nm 65nm 40nm 28nm 22nm 16/14nm 10nm 7nm 5nm 2nm These Benefits are ADDITIVE & COMPLEMENTARY to o
Slide 12: MST technology focus areas
MST-SP, MST SPX for BCD technology focus areas MST for RF-SOI MST for Advanced Nodes MST for DRAM Atomera 12
Slide 13: MST optimizes AI performance
MST optimizes AI performance ► AI algorithms are driving unparalled computing demands ▪ Exceeding ideal single chip silicon area which impacts yield ► Heterogenous chiplet architectures solve this problem ► Small chiplet designs can be optimized by process node ► MST’s ability to enhance mature node
Slide 14: Strategic Marketing Agreement
Strategic Marketing Agreement ► Joint marketing agreement with major ► Leverages partner’s sales and marketing semiconductor equipment maker resources ► Focused on Gate-All-Around transistors ► Partnership may extend into other application areas ► Enables solutions that are more validated so faster
Slide 15: GAA Opportunity
GAA Opportunity ► MST provides benefits in multiple areas for Gate-All-Around transistors From: IMEC MST in S/D contact MST in source/drain MST in the channel MST in backside contact Source: S. Mukesh, Electronics (2022) Source: IMEC Atomera Incorporated 15
Slide 16: MST-SPX
MST-SPX ► Atomera introduced MST-SP in 2022 ▪ Market leading 5V Rsp vs BVdss performance ▪ Allows higher efficiency, smaller size ► MST-SPX targets 5-48V ▪ Area of highest customer interest ► MST achieves best in class performance ▪ MST-SPX beat all published results ▪ Simulations predict up to 20%
Slide 17: Variability reduction with MST
Variability reduction with MST ► High variability between transistors is a significant issue ▪ A big driver of variability is Random Dopant Fluctuation (RDF) Vt difference in a matched transistor pair ▪ Some transistors are designed larger to account for variability ▪ This increases costs and limits
Slide 18: RFSOI LNA
RFSOI LNA ► Macro factors affecting handset design ▪ New mobile phones want to move from 4 to 6 carrier aggregation channels ▪ New freq bands opening for 5G and 6G cellular ► LNAs (Low Noise Amplifiers) ▪ Receiver circuit used in mobile phones ▪ Must turn on frequently to monitor for signals ▪ Can b
Slide 19: MST for GaN/Si
MST for GaN/Si ► Atomera provides modified Si substrates incorporating MST layers GaN device layers ► GaN growth at various US locations (RF, power, mLED) GaN enabling ► Physical characterization indicates layers fewer defects in GaN device layer Stress-relief layers ► Electrical characterization in
Slide 20: GaN/Si crystal quality improvement
GaN/Si crystal quality improvement 1,400 1,200 14% reduction X-ray confirms crystal quality improvement with MST ------- 1,000 Collaboration with Sandia’s CINT to validate benefits XRD FWHM (arcsec) 800 13% reduction 600 GaN/Si GaN/Si with 400 control MST GaN/Si GaN/Si with control 200 MST 0 AlN (00
Slide 21: Compound Semiconductors
Compound Semiconductors ► Compound semiconductor market growing rapidly ▪ GaN is one example ► Poor wafer substrate quality causes manufacturing challenges ► Atomera’s MST may help to solve this problem ► Early experiments of GaN on MST show promising results Atomera 21
Slide 22: Royalty Opportunity
Royalty Opportunity ► ~410 wafer fabs operating worldwide ► Adoption of MST in one fab can make Atomera profitable from royalties alone ▪ 2025 non-GAAP OPEX guidance is ~$17M Example 1 | Worldwide Average Fab Example 2 | Leading Foundry, 28nm Fab Monthly Fab Capacity1 Monthly Fab Capacity 46,240 80,
Slide 23: MST Customer Business Opportunity
MST Customer Business Opportunity ► Foundry economics Wafer GM$ MST Wafer Price GM% Increase Royalty Cost 28nm HP wafer $ 3,300 45% $ - $ - $ 1,815 28nm HP+ wafer $ 3,450 45% $ 68 $ - 5% higher price for +15% performance boost 28nm HP wafer with MST $ 3,600 47.0% $ 208 $ 72 $ 1,907 30% performance b
Slide 24: Financial Review
Financial Review Atomera Incorporated 24
Slide 25: Summary
Summary ► High margin, recurring revenue financial model ► Strong technology, patent position, and balance sheet ► Traction with many top industry players and growing licensee base ► Ramping commercial license revenues Atomera Incorporated 25
Slide 26: Thank You
Thank You Atomera Incorporated 26
Slide 27: Backup Slides
Backup Slides Atomera Incorporated 27
Slide 28: Customer Engagement Model
Customer Engagement Model Customer Wafer Manufacturing Standard customer engagement Atomera MST® Deposition Customer MST® Deposition Planning Setup Integration Installation Qualification Production Phase Joint development 1 Atomera MST® Deposition Customer MST® Deposition JDA Completion Planning Set
Slide 29: MST-SP
MST-SP ► MST-SP is a highly-engineered asymmetric power device ▪ Uses MST to enhance Idlin and precisely control dopant profiles ► Improves 5V power devices G ▪ Lower RSP B S D ▪ Can be traded for up to 20% smaller area ► Targeted for rapidly-growing PMIC market 29
Slide 30: 5V Transistors – Critical and Growing Market
5V Transistors – Critical and Growing Market ► Targeted at rapidly-growing PMIC (Power Management IC) market ▪ Power devices can be up to 80% of PMIC die area ► All ICs need stable, regulated power ▪ Across battery charge level, lifetime degradation, and load ▪ Across usage modes – DVS (Dynamic Volt
Slide 31: MST-SPX targeting power devices
MST-SPX targeting power devices ► Targets higher voltage (5-40V) product area Rsp vs. BVdss ► Strong customer demand for solutions Rsp vs. BV Plot Si control ► MST brings significant improvement Si control ▪ Early results showing gains in many areas 38% MST Better -38% ▪ Allows manufacturers to shri
Slide 32: Example: Use Of 5V Transistor In Apple iPhone13
Example: Use Of 5V Transistor In Apple iPhone13 13 of 25 IC’s in Apple iPhone13 Pro use 5V transistors ▪ iPhone 13 Pro teardown by Tech Insigths ▪ 5V transistor assessment by Atomera Reference https://www.techinsights.com/blog/teardown/apple-iphone-13-pro-teardown?utm_source=Prospect+Email&utm_mediu
Slide 33: 5V MST-SP Product – Value Proposition
5V MST-SP Product – Value Proposition ► Industry best performance at 180nm (Rsp) ▪ Based on measured silicon data ▪ Scalable to smaller process nodes Gate G B S D ► Meets all reliability requirements Source Drain ▪ Breakdown Voltage (BVDSS) > 10.5V MST MST ► Significant cost savings, performance ben
Slide 34: Atomera MSTcad
Atomera MSTcad ► Leading semiconductor companies use TCAD to model manufacturing processes ▪ MSTcad is an add-on for MST ► MSTcad can speeds up the time needed to evaluate multiple MST integration options ► Lowers cost of MST evaluation ► Speeds time to successful wafer runs ► Fewer wafer runs lead
Slide 35: MST enables legacy capacity expansion
MST enables legacy capacity expansion ► MST provides 30% performance advantage ▪ 0.13u analog design ▪ MST vs control silicon ► Enables a die shrink of 15-20% ► Smaller die means more manufacturing capacity ▪ Without the cost of building a new fab Atomera Incorporated 35
Slide 36: MST 28nm benefits
MST 28nm benefits MST shows 30% ► Performance improvements due to MST can be higher performance traded for area reduction ► 28nm PDK SPICE model used to showcase: ▪ Logic scaling with MST shows 22-25% area reduction • Using a NAND2 gate ▪ Analog scaling with MST shows up to 21% area reduction ► Impl
Slide 37: MST for High-k metal gate (HKMG) transistors
MST for High-k metal gate (HKMG) transistors ► MST enhances HKMG transistor performance and reliability* ▪ Reduced stress induced leakage current (SILC) enabling reliability improvement ▪ 23% long-channel mobility enhancement ▪ 2.7x lower gate leakage SILC e- mobility JG vs. EOT * Professor Suman Da
Slide 38: MST: Mears Silicon Technology
MST: Mears Silicon Technology Quantum Engineered Silicon Partial Monolayers of MST Enhanced Oxygen in Silicon Transistors Supported by Major Semiconductor Tool Suppliers Atomera Incorporated 38
Slide 39: Atomera state of the art research center
Atomera state of the art research center ► Epi deposition facility ▪ 300mm Epi deposition ▪ 200mm Epi deposition ▪ Wafer cleaning equipment ▪ Metrology tools ▪ Advanced wafer handling ▪ World class clean room facility ► Available to deliver customer wafers Epi Deposition Tool Atomera Incorporated 39
Slide 40: Atomera MSTcad Progress
Atomera MSTcad Progress ► Leading semiconductor companies use TCAD ► MST is modelled with a TCAD add-on called MSTcad ► These plots show silicon verification of MSTcad simulations ► Enables good electrical match-up for 5V NMOS and MST SP ► Should speed time to successful results with customers Atome
Slide 41: MST1 vs MST2
MST1 vs MST2 ► MST1 ▪ Blanket technology ▪ Easy to integrate ▪ Deposited at beginning of mfg process ▪ Degraded by high heat in STI/Well module ▪ Faster time to market for low heat processes ▪ Used for FinFET, RFSOI, newer process nodes ► MST2 ▪ Selective technology • Integrated after STI/Well so av