Slide 1: High-Performance Memories for Packet Processing
High-Performance Memories for Packet Processing Chris Johnson Global DRAM Applications Engineering Manager ©2012 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products, and/or specifications are subject to
Slide 2: High Performance Networking Memories
High Performance Networking Memories Requirements • Low-tRC/high access rate Trends • High bandwidth • Low-tRC architectures • Density and Scalability • Managed DRAM • Low pin-count • SerDes interfacing • Small footprint • 2.5/3D integration • Low power consumption • Photonics • Reasonable system co
Slide 3: Commodity DRAM Drivers
Commodity DRAMDRAM Commodity Drivers (DDR1/2/3/4) Drivers Volume Die Size Primary driver Increased die per wafer Equates directly to yield Improved yield Manufacturing efficiencies Test times Tooling Back end flexibility Amortized R&D cost Appropriate Design Margin IO Count Commodity F
Slide 4: Solutions for High Performance
Solutions for High Performance Reduced Page Size Faster core timing Lower power Increases die size Beef Up Power Bussing Eliminates tRRD and tFAW type restrictions Adds metal count or die size Reduce Turn Times Change functionality or architecture Added posting registers Adds die siz
Slide 5: RL3 Solves Access Rate Gap
RL3 Solves Access Rate Gap Reduce Random Access (Row Cycle Time Fragments the array Reduced digit line length Bus Turn-around Time Add WRITE registers Eliminate internal bus contention Eliminate RAS Chain Limitations Move to flip chip Increased power bussing ©2012 Micron Technology, Inc.
Slide 6: Bus Turnaround Delay Effect on Bandwidth
Bus Turnaround Delay Effect on Bandwidth RL3 Delivers Sustained Bus Utilization Under Networking Workloads RL3-2133 BL8 RL2-1066 CIO BL8 DDR3-2133 BL8 CL=13 2,133 1,867 Bandwidth per Data Pin (Mb/s) 1,600 1,333 1,067 800 533 267 0 0.01 0.10 1.00 10.00 100.00 Read/Write Ratio Key Parameters • <8ns tR
Slide 7: Process Characteristics
Process Characteristics DRAM Process Create really good capacitors Memory Cells Limits Speed Increases Power Limited Metal Layers Low Cost Logic Process Low Capacitance High speed Low Power Large number of metal steps Design flexibility ©2012 Micron Technology, Inc. | 7
Slide 8: Hybrid Memory Cube (HMC)
Hybrid Memory Hybrid Cube Memory Cube (HMC) Introduction of Managed DRAM Through-Silicon Vias (TSV) DRAM Abstraction DRAM Protocol DRAM DRAM Many Buses > 1Tb/s Processor Logic Die High Speed Links Reduced Pin count Increased Bandwidth Note: Tb/s = Terabits / second ©2012 Micron Technology, Inc. | 8
Slide 9: HMC Architecture
HMC Architecture Logic Base Vault Control Vault Control Vault Control Vault Control Add advanced switching, Memory Control optimized memory control and simple interface to host Crossbar Switch processor(s)… Link Interface Link Interface Link Interface Link Interface Controller Controller Controller
Slide 10: 2.5D/2D/MCM System/3D
2.5D/2D/MCM System/3D 2.5D SOC IP Block DRAM Stack Si Interposer(2.5D) MCM substrate (2D) 3D Opens New Possibilities ▶ DRAM IP Block part of SOC Can be tailored to SOC interface requirement DRAM Stack Emulate another DRAM technology interface if necessary Manage DRAM arrays e.g. 64GB/s Paralle
Slide 11: Micron
Micron Focused on Memory | Engineered for Innovation