Slide 1: RISC-V Vector Extension Webinar I
RISC-V Vector Extension Webinar I July 13th, 2021 Thang Tran, Ph.D. Principal Engineer
Slide 2: Andes Technology Corporation: Who We Are
Andes Technology Corporation Who We Are Pure-play CPU CPU IP Vendor RISC-V Founding Premier Member Major Open-Source Contributor/Maintainer RISC-V Ambassador 16-year-old Running Task Groups Public Company TSC Vice Chair Director of the Board Quick Facts 100+years NL 80% USA FR IL BJ KR JP SH CPU Exp
Slide 3: Andes Technology Corporation Overview
Andes Technology Corporation Overview Andes Highlights •Founded in March 2005 in Hsinchu Science Park, Taiwan, ROC. •World class 32/64-bit RISC-V CPU IP public company •Over 200 people; 80% are engineers; R&D team consisting of Silicon Valley veterans •TSMC OIP Award “Partner of the Year” for New IP
Slide 4: V5 Adoptions: From MCU to Datacenters
V5 Adoptions: From MCU to Datacenters • Edge to Cloud: − ADAS − Datacenter AI accelerators − AIoT − SSD: enterprise (& consumer) − Blockchain − 5G macro/small cells − FPGA − MCU − Multimedia − Security − Wireless (BT/WiFi) 5G Macro • 1 to 1000+ core • 40nm to 5nm • Many in AI Copyright© 2020 Andes T
Slide 5: Webinar I - Agenda
Webinar I - Agenda • Andes overview • Vector technology background – SIMD/vector concept – Vector processor basic • RISC-V V extension ISA – Basic – CSR – Memory operations – Compute instructions • Sample codes – Matrix multiplication – Loads with RVV versions 0.8 and 1.0 • AndesCore™ NX27V introduc
Slide 6: Terminology
Terminology • ACE: Andes Custom Extension • ISA: Instruction Set Architecture • CSR: Control and Status Register • GOPS: Giga Operations Per Second • SEW: Element Width (8-64) • GFLOPS: Giga Floating-Point OPS • ELEN: Largest Element Width (32 or 64) • XRF: Integer register file • XLEN: Scalar regis
Slide 7: RISC-V & RVV Background
RISC-V & RVV Background • An open processor architecture started by UC Berkeley – Compact, modular, extensible • RISC-V International (formerly RISC-V Foundation) – RISC-V Foundation formed in 2015 to govern its growth – 750+ members including industry and research institute/university • RISC-V Vect
Slide 8: RISC-V V Spec Status
RISC-V V Spec RISC-V Status V Spec Status • Version 1.0-rc1 was published in June 2021 • Note from the spec: “When finally approved and the release candidate tag is removed, version 1.0 is intended to be sent out for public review as part of the RISC-V International ratification process. Version 1.0
Slide 9: Vector technology background
Vector technology background Copyright© 2020 Andes Technology Corp. 9
Slide 10: Flynn's Classification
Flynn’s Classification • Instruction Stream − Sequence of Instructions read from memory • Data Stream − Operations performed on the data in the processor • SIMD is the most interesting which is the basic for: Microprocessors − MMX, SSE, SSE2-5, AVX − Altivec − Neon DSP Number of Data Streams Graphic
Slide 11: Why SIMD?
Why SIMD? • Single 32-bit Microprocessor – One 32-bit element per instruction • 512-bit SIMD processor – 16 32-bit elements per instruction – 32 16-bit elements per instruction – 64 8-bit elements per instruction. If the SIMD processor clock frequency is at 1 GHz, then the performance is 64 GOPS • I
Slide 12: Parallel Processing
Parallel Processing • Time-space duality: – Array processor: Instruction operates on multiple data elements at the same time – multi-thread, multi-core – Vector processor: Instruction operates on multiple data elements in consecutive time steps – pipeline of SIMD execution ARRAY PROCESSOR VECTOR PRO
Slide 13: Intel MMX, SSE, SSE2, AVX
Intel MMX, SSE, SSE2, AVX • MMX (1997) adds 57 new integer instructions, 64-bit registers – 8 of 8-bit, 4 of 16-bit, 2 of 32-bit, or 1 of 64-bit (reuse 8FP registers – FP and MMX cannot mix) – Number of elements is defined in the opcode, only consecutive memory load/store is allowed – Move, Add, Sub
Slide 14: Vector Extension Processor Overview
Vector Extension Processor Overview A Vector Element v31 v31 r31 f31 Vector r31 f31 Meta Data RISC-V CPU One Lane. Usually less VLEN Lanes than Vector Elements (Lanes/VFUs Parallelism achieved by: timeshared) • Multiple Lanes • Multiple VFUs per Lane (e.g., L/S, +, x) • Individual VFUs are pipelined
Slide 15: Vector Instruction Chaining
Vector Instruction Chaining • Independent functional units are needed – Partial data of an instruction can be forwarded Vector Register File and operations are scheduled to be executed in parallel – Data chaining can happen only if the instructions operate on multiple SIMD widths chain chain • VLEN=
Slide 16: Chaining – Vector Unit Structure
Chaining – Vector Unit Structure • Four lanes, 4 functional units to fetch/execute independent data 16 elements, 4 lanes: - Elements 0-3 - Elements 4-7 - Elements 8-11 - Elements 12-15 Functional Unit Copyright© 2020 Andes Technology Corp. 16
Slide 17: Chaining
Chaining • 32 elements, 8 lanes = 8 units to fetch/execute 8 independent elements – vld: fetch data 32 elements in 4 clock cycles, 8 elements per cycle – Vector add/mult: each vector instruction passes through the functional units 4 times 8 lanes, 8 LS units 8 lanes, 8 vector MUL units 8 lanes, 8 ve
Slide 18: Vectorize Loop Iterations
Vectorize Loop Iterations • X and Y are vectors, a is scalar, n is a large number C Code • For N=64, dynamic instructions – Processor = 64x9 + 2 = 578: – Vector = 6 (5 vectors and 1 scalar) Vector Code Processor/SIMD Code scalar vectors RAW Dependencies Operate on 64 elements From: Patterson, D., CS
Slide 19: Advantages of Vector Architecture
Advantages of Vector Architecture • From Spec92fp* – Static Instructions: scalar/vector = 4.5X – Dynamic Instructions: scalar/vector = 23.8X – Operations: scalar/vector = 1.4X (the extra operations are loop overheads) • Most efficient way for data parallel processing – High computation throughput (o
Slide 20: Example: Cray 1
Example: Cray 1 • Scalar and vector mode • 8 64-element vector registers – SEW = 64-bit – VLEN = 64x64 = 4096-bit • 8 64-bit scalar registers • 8 24-bit address registers • 16 memory banks – Bank latency = 11 cycles – Sustain 16 parallel accesses to different banks • 77 x 104 x 57 inches, 5.5 tons,
Slide 21: Strip Mining
Strip Mining • When the size of vector > VLMAX 1st Iteration - odd size – size MOD(VLMAX) = the number of elements in the MOD(VLMAX) piece first iteration – n/VLMAX = number of iterations for each VLMAX time 2nd Iteration VLMAX elements • Example of application VL = 200 elements – 200 MOD(64) = 8 el
Slide 22: Technical Challenges of Vector Architecture
Technical Challenges of Vector Architecture • Complexity of vector register file (VRF) with VLEN=512-bit – Complexity of handling read and write ports with multiple lanes are much more expensive in VRF in comparison to scalar or FP register files – Performance is related to the number of read and wr
Slide 23: Applications of Vector Processing
Applications of Vector Processing • Scientific computations (astrophysics, atmospheric, ocean modeling, bioinformatics, physics, biomolecular simulation, chemistry, fluid dynamics, material sciences, quantum chemistry) • Engineering computations (computer vision and image, data mining and data inten
Slide 24: Vectorizing Media Processing
Vectorizing Media Processing • Kernel • Vector length − Matrix transpose/multiply − # vertices at once − DCT (video, communication) − image width − FFT (audio) − 256-1024 − Motion estimation (video) − image width, iw/16 − Gamma correction (video) − image width − Haar transform (media mining) − image
Slide 25: Overview of NX27V
Overview of NX27V • AndeStar V5 architecture: – RV64GCN+ Andes V5 Extensions – RV Vector extension (RVV) • 5-stage pipeline, single-issue – Optional branch prediction • I/D caches – Caches: 8KB to 64KB – I$/D$ prefetch – HW unaligned load/store accesses – 16 non-blocking outstanding data accesses •
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Slide 27: Thank you!
Thank you!