Slide 1: RISC-V Vector Extension Webinar II
RISC-V Vector Extension Webinar II August 3th, 2021 Thang Tran, Ph.D. Principal Engineer
Slide 2: Webinar II - Agenda
Webinar II - Agenda • Andes overview • Vector technology background – SIMD/vector concept – Vector processor basic • RISC-V V extension ISA – Basic – CSR • RISC-V V extension ISA – Memory operations – Compute instructions • Sample codes – Matrix multiplication – Loads with RVV versions 0.8 and 1.0 •
Slide 3: Terminology
Terminology • ACE: Andes Custom Extension • ISA: Instruction Set Architecture • CSR: Control and Status Register • GOPS: Giga Operations Per Second • SEW: Element Width (8-64) • GFLOPS: Giga Floating-Point OPS • ELEN: Largest Element Width (32 or 64) • XRF: Integer register file • XLEN: Scalar regis
Slide 4: RISC-V V Extension ISA Basic
RISC-V V Extension ISA Basic Copyright© 2020 Andes Technology Corp. 4
Slide 5: Vector Register ISA
Vector Register ISA • Vector-Register ISA Definition: − All vector operations are between vector registers (except for load and store). This is in contrast with Vector-Memory ISA where all vector operations are on data memory − Vector load-store unit fetches and stores the memory data to/from vector
Slide 6: Vector Processing ISA Basic
Vector Processing ISA Basic Scalar Standard scalar RISC-V ISA Scalar FP Standard floating-point RISC-V ISA ALU Mult s.int 8 .vv Macc u.int 16 .vx Saturate masked Vector ALU Mask fp 32 .vi Overflow unmasked Permute 64 Divide Custom Int4 4 8 load s.int 8 16 constant masked Vector Memory store u.int 16
Slide 7: Notations
Notations • Register references – vs1, vs2, vd – source and destination vector registers, VRF – rs1, rs2, rd – source and destination integer registers, XRF – fs1, fs2, fd – source and destination floating point registers, FRF • Register numbers – v0, v1, …, v30, v31 – vector register numbers (addre
Slide 8: Vector Processor Overview - Block Diagram
Vector Processor Overview - Block Diagram Memory multi banks Vector Load/Store FP MAC unit 0 MVL Element FP misc unit 1 MVL Element 2 MVL Element FP divide unit Vector Registers 3 MVL Element … … Integer ALU … … … … Integer MAC unit … … R0 30 MVL Element R1 Integer divide unit 31 MVL Element R2 Scal
Slide 9: Vector Processor Microarchitecture Features
Vector Processor Microarchitecture Features Memory Many types of memories can be implemented multi banks - Cache memory, uncache memory, and local vector memory Execution queues for out-of-order execution Central control for VRF read/write ports Vector Load/Store FP MAC unit 0 MVL Element FP misc un
Slide 10: RISC-V V Extension ISA CSR
RISC-V V Extension ISA CSR Copyright© 2020 Andes Technology Corp. 10
Slide 11: Vector CSR Registers
Vector CSR Registers Address Privilege Name Description 0x008 URW vstart Vector start position 0x009 URW vxsat Fixed-Point Saturate Flag 0x00A URW vxrm Fixed-Point Rounding Mode 0x00F URW vcsr Vector control and status register 0xC20 URO* vl Vector length 0xC21 URO* vtype Vector data type register 0
Slide 12: CSR – Vector Execution Fixed Point Register
CSR – Vector Execution Fixed Point Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved sat • vxsat – Vector Fixed-Point Saturation Flag Register – single bit to indicate that saturated value was written to destination vector register 31 30 29 28 27
Slide 13: CSR – Vector Execution Floating-Point Register
CSR – Vector Execution Floating-Point Register • The vector processor uses the fflags and frm from the FPU – fflags[4:0]: floating-point accrued exception flags – frm[2:0]: floating-point rounding modes Copyright© 2020 Andes Technology Corp. 13
Slide 14: CSR – Vector Type Register (vtype)
CSR – Vector Type Register (vtype) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vill reserved vsew vlmul vma vta • vlmul[2:0] – grouping of vector registers, 2x, 4x, 8x, or fraction of vector register, 1/2, 1/4, 1/8 – 000: no grouping, 32 vector registers, VL
Slide 15: LMUL – Registers Grouping
LMUL – Registers Grouping LMUL=1 LMUL=4 v31 v28 v30 v24 v29 … v28 v4 … LMUL=2 v0 … v30 … v28 … … LMUL=8 v3 … v24 v2 … v16 v1 v2 v8 v0 v0 v0 • LMUL=2, instructions with odd register are illegal instructions • LMUL=4, vector registers are incremented by 4, else illegal instructions • LMUL=8, only v0,
Slide 16: LMUL – Fractional Registers
LMUL – Fractional Registers elements 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LMUL=1 LMUL=1/2 LMUL=1/4 LMUL=1/8 • LMUL=1/2, load data into half vector register, then perform vector double operations to expand data to the whole register • LMUL=1/4, using v
Slide 17: Vector Register Programming Model
Vector Register Programming Model • 32 vector registers – 5-bit • VLEN = The width of each vector register[i] in power of 2 • Version 0.7: FPU cannot shares the vector registers Scalar FP Register Register Vector Registers R31 F31 V31 . . . . . . . . . R0 F0 V0 [VLMAX-1] … [2] [1] [0] Vector Length
Slide 18: Vector Register 64-bit Elements
Vector Register 64-bit Elements Scalar FP Register Register Vector Registers R31 F31 V31 . . . . . . . . . R0 F0 V0 7 6 … … 2 1 0 element # [VLMAX-1] … [2] [1] [0] Vector Length Register VLEN VLEN=512b, SEW=64b Copyright© 2020 Andes Technology Corp. 18
Slide 19: Vector Register 32-bit Elements
Vector Register 32-bit Elements Scalar FP Register Register Vector Registers R31 F31 V31 . . . . . . . . . R0 F0 V0 15 14 … … 2 1 0 element # [VLMAX-1] … [2] [1] [0] Vector Length Register VLEN VLEN=512b, SEW=32b Copyright© 2020 Andes Technology Corp. 19
Slide 20: Vector Register 16-bit Elements
Vector Register 16-bit Elements Scalar FP Register Register Vector Registers R31 F31 V31 . . . . . . . . . R0 F0 V0 31 30 … … 2 1 0 element # [VLMAX-1] … [2] [1] [0] Vector Length Register VLEN VLEN=512b, SEW=16b Copyright© 2020 Andes Technology Corp. 20
Slide 21: Vector Register 8-bit Elements
Vector Register 8-bit Elements Scalar FP Register Register Vector Registers R31 F31 V31 . . . . . . . . . R0 F0 V0 63 62 … … 2 1 0 element # [VLMAX-1] … [2] [1] [0] Vector Length Register VLEN VLEN=512b, SEW=8b Copyright© 2020 Andes Technology Corp. 21
Slide 22: Element Numbering, LMUL=2
Element Numbering, LMUL=2 • Straight forward numbering, increment sequentially • The numbering is important for mask and permutation operations Vm*n 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1
Slide 23: Vector Register 8-bit Elements, LMUL
Vector Register 8-bit Elements, LMUL Vector Registers V31 . . V8 V7 511 510 … … … 449 448 V6 447 446 … … … 385 384 V5 383 382 … … … 321 320 V0, LMUL=8 V4 319 318 … … … 257 256 V0, LMUL=4 V3 255 254 … … … 193 192 V0, LMUL=2 V2 191 190 … … … 129 128 V1 127 126 … … … 65 64 V0 63 62 … … … 1 0 element #
Slide 24: LMUL=8 and Chaining Example
LMUL=8 and Chaining Example Cycles: 1 2 3 4 5 6 7 8 9 10 vmul v0, v8, v16 X1 X2 Vector length: VLEN * LMUL v1, v9, v17 X1 X2 • LMUL=1 → 512 bits • LMUL=8 → 4096 bits V0~V7 group 1 ……… … … … … … V8~V15 group 2 V16~V23 group 3 v7, v15, v23 X1 X2 V24~V31 group 4 vadd v24, v0, v8 X1 v25, v1, v9 X1 ……… …
Slide 25: Vector Mask – Conditional or Predicate Execution
Vector Mask – Conditional or Predicate Execution • v0 is used for vector mask, single mask for all LMUL values – 1 mask bit for each element • 0 – mask (mask-off), no write to destination vector elements, cannot have exception • 1 – unmask – The mask is enabled for each vector instruction with inst[
Slide 26: CSR - Vector Length Register (vl)
CSR - Vector Length Register (vl) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved vl[VLMAX*8-1:0] • vl is the number of elements for vector operations – Updated by vsetvl(i) instruction along with the vtype CSR • vl is set to VLMAX if the set value is g
Slide 27: CSR Vector Instruction – vsetvli/vsetvl
CSR Vector Instruction – vsetvli/vsetvl • Two vector CSRs are updated by single instruction – vsetvli rd, rs1, vtypei // vl=rs1 (which is also AVL, application vector length), rd=AVL – vsetvl rd, rs1, rs2 // rd = avl • CSR updates: – csr.vtype = vtypei or rs2 • {m1}, m2, m4, m8, mf2, mf4, mf8 – sett
Slide 28: Sample Codes for LMUL and SEW Manipulation
Sample Codes for LMUL and SEW Manipulation • VLEN=512b, e8 to e32 elements for 16 elements vl=16 vsetvli t0, zero, e8, mf4 // set SEW=8b, LMUL=1/4, VLMAX=64/4=16 elements sew=8 vle8.v v8, (a2) // load 16 8b elements sew=8b vsext.vf4 v8, v8 // Signed extended 16 8b elements to 32b elements lmul=1/4 v
Slide 29: Optimized codes for Load and Signed Extension
Optimized codes for Load and Signed Extension • VLEN=512b, e8 to e32 elements for 16 elements vsetvli t0, zero, e32 // set SEW=32b, LMUL=1, vl=512/32=16 elements vle8.v v8, (a2) // load 16 8b elements, vle16.v or vle32.v is always 16 elements vsext.vf4 v8, v8 // Signed extended 16 8b elements to 32b
Slide 30: Sample Code for Large Data Set
Sample Code for Large Data Set • VLEN=512b, e8 to e32 elements for 128 elements vsetvli t0, zero, e32, m8 // set SEW=32b, LMUL=8, vl=512b*8/32b=128 elements vle8.v v6, (a2) // load 128 8b elements into 2 vector registers, v6-v7 vsext.vf4 v0, v6 // Signed extended 128 8b elements to 32b elements vadd
Slide 31: CSR - Vector Byte Length
CSR - Vector Byte Length 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved vlenb = 64 • Vector register length in bytes, vlenb = VLEN/8 – Design time constant, vlenb = 512/8 = 64 – Read-only CSR, constant value, hardwired – A configuration CSR Copyright©
Slide 32: CSR – Vector Start Index Register (vstart)
CSR – Vector Start Index Register (vstart) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved vstart[VLMAX*8-1:0] • Initialize to zero • vstart is the index of element that causes the trap on vector instruction • When return from trap, the vector execution
Slide 33: Valid Vector Range
Valid Vector Range Behavior for destination element i 0 < i < vstart Unchanged vstart <= i < vl Updated if v0.mask[i] enabled, unchanged if not mta exception vl <= i < VLMAX Unchanged, vta exception VLMAX-1 vl-1 Masked elements vstart 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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Slide 35: Thank you!
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