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ARM — Hot Chips 28 (August 2016)
31 slides from ARM's conference presentation, August 2016
Slide 1: The Bifrost GPU architecture and the ARM Mali-G71 GPU
The Bifrost GPU architecture and the ARM Mali-G71 GPU Jem Davies ARM Fellow and VP of Technology Hot Chips 28 Aug 2016
Slide 2: Introduction to ARM Soft IP
Introduction to ARM Soft IP ARM licenses Soft IP cores (amongst other things) to our Silicon Partners They then make chips and sell to OEMs, who sell consumer devices “ARM doesn’t make chips”… We provide all the RTL, integration testbenches, memories lists, reference floorplans, example synt
Slide 3: ARM Mali: The world's #1 shipping GPU
ARM Mali: The world’s #1 shipping GPU 750M 65 27 Mali-based 140 Total new Mali licenses in GPUs shipped in 2015 Total licenses licensees FY15 Mali is in: Mali graphics based IC shipments (units) 750m ~75% ~50% ~40% 400m 550m of of of 150m DTVs… tablets… smartphones <50m 2011 2012 2013 2014 2015 3 ©
Slide 4: ARM Mali graphics processor generations
ARM Mali graphics processor generations Mali-G71 BIFROST … GPU Unified shader cores, scalar ISA, clause execution, full coherency, Vulkan, OpenCL MIDGARD Mali-T600 GPU series Mali-T700 GPU series Mali-T800 GPU series Unified shader cores, SIMD ISA, OpenGL ES 3.x, OpenCL, Vulkan Presented at HotChips
Slide 5: Bifrost features
Bifrost features Leverages Mali’s scalable architecture Scalable to 32 shader cores 20% Scalable to 32 Higher energy Shader cores Major shader core redesign efficiency* New scalar, clause-based ISA New quad-based arithmetic units New geometry data flow Reduces memory bandwidth and foot
Slide 6: Bifrost features
Bifrost features Leverages Mali’s scalable architecture Scalable to 32 shader cores 20% Scalable to 32 Higher energy Shader cores Major shader core redesign efficiency* New scalar, clause-based ISA New quad-based arithmetic units New geometry data flow Reduces memory bandwidth and foot
Slide 7: Bifrost GPU design
Bifrost GPU design Driver Software Up to 32 shader cores supported Shader Shader Shader Shader Job Manager Core 0 Core 1 Core 2 Core 31 GPU Fabric L2 Cache L2 Cache L2 Cache L2 Cache Tiler MMU Segment Segment Segment Segment ACE Memory Bus ACE Memory Bus ACE Memory Bus ACE Memory Bus 7 © ARM2016
Slide 8: Bifrost features
Bifrost features Leverages Mali’s scalable architecture Scalable to 32 shader cores 20% Scalable to 32 Higher energy Shader cores Major shader core redesign efficiency* New quad-based arithmetic units New scalar, clause-based ISA New geometry data flow Reduces memory bandwidth and foot
Slide 9: Shader core improvements
Shader core improvements Driver Software Shader Shader Shader Shader Job Manager Core 0 Core 1 Core 2 Core 31 GPU Fabric L2 Cache L2 Cache L2 Cache L2 Cache Tiler MMU Segment Segment Segment Segment ACE Memory Bus ACE Memory Bus ACE Memory Bus ACE Memory Bus 9 © ARM2016
Slide 10: Mali-G71 shader core design
Mali-G71 shader core design Compute Frontend Fragment Frontend Quad Creator Quad Creator Execution Execution Execution Engine 0 Engine 1 Engine 2 Quad Quad Manager ZS Memory Quad State Quad State Quad State Control Shader Core Fabric Load/store Attribute Varying Texture Blender & Depth & Unit Unit U
Slide 11: Quad execution
Quad execution Compute Frontend Fragment Frontend Quad Creator Quad Creator Execution Execution Execution Engine 0 Engine 1 Engine 2 Quad Manager ZS Memory Quad State Quad State Quad State Shader Core Fabric Load/store Attribute Varying Texture Blender & Depth & Unit Unit Unit Unit Tile Access Stenc
Slide 12: Recap: SIMD vectorization
Recap: SIMD vectorization Lane 0 Lane 1 Lane 2 Lane 3 Midgard GPUs use SIMD vectorization One thread at a time executes in each pipeline stage T0.x T0.y T0.z Idle Cycle 1 Each thread must fill the width of the hardware T1.x T1.y T1.z Idle Cycle 2 T2.x T2.y T2.z Idle Cycle 3 Sensitive to shad
Slide 13: Quad vectorization
Quad vectorization Lane 0 Lane 1 Lane 2 Lane 3 Bifrost uses quad-parallel execution Four scalar threads executed in lockstep in a “quad” T0.x T1.x T2.x T3.x Cycle 1 One quad at a time executes in each pipeline stage Each thread fills one 32-bit lane of the hardware T0.y T1.y T2.y T3.y Cycle
Slide 14: Execution engine
Bifrost execution engine Executes quad-parallel scalar operations 4x32-bit multiplier FMA Main Regs Read 4x32-bit adder ADD Adder includes special function unit Smaller and more area efficient Temp Registers FMA Simplified layout eases compilation Better scheduling in today’s code Be
Slide 15: Execution engine: Special arithmetic ops
Bifrost execution engine: Special arithmetic ops Special function hardware is smaller than Main Regs Read Midgard VLUT equivalent Many transcendental functions supported Special functions provide building blocks for compiled shader code Temp Registers FMA Part of the built-in function librar
Slide 16: Execution engine: Functional units
Bifrost execution engine: Functional units Retains support for smaller width data types 2x performance for FP16 useful for pixel shaders Main Regs Read int8 int8 int8 int8 8-bit integers Temp Registers FMA int16 int16 16-bit integers int32 32-bit integers float16 float16 16-bit floating point AD
Slide 17: Bifrost features
Bifrost features Leverages Mali’s scalable architecture Scalable to 32 shader cores 20% Scalable to 32 Higher energy Shader cores Major shader core redesign efficiency* New quad-based arithmetic units New scalar, clause-based ISA New geometry data flow Reduces memory bandwidth and foot
Slide 18: Clause execution
Clause execution A group of instructions which executes atomically Architectural state visible after clause completion Bypass path registers exposed to the compiler Non-deterministic instructions on clause boundaries 18 © ARM2016
Slide 19: Bifrost shader clause example
Bifrost shader clause example Linear Source LOAD.32 r0, [r10] FADD.32 r1,r0,r0 FADD.32 r2,r1,r1 FADD.32 r3,r2,r2 FADD.32 r4,r3,r3 FADD.32 r3,r3,r4 FADD.32 r0,r3,r3 STORE.32 r0, [r10] 19 © ARM2016
Slide 20: Bifrost shader clause example
Bifrost shader clause example Linear Source Basic Clause Compile Load is variable LOAD.32 r0, [r10] length, so clause { FADD.32 r1,r0,r0 must be split LOAD.32 r0, [r10] FADD.32 r2,r1,r1 } FADD.32 r3,r2,r2 from use of r0 FADD.32 r4,r3,r3 wait(load) { FADD.32 r3,r3,r4 Next clause uses FADD.32 r1,r0,r0
Slide 21: Bifrost shader clause example
Bifrost shader clause example Linear Source Basic Clause Compile Optimized Clause Compile Load is variable LOAD.32 r0, [r10] length, so clause { { FADD.32 r1,r0,r0 must be split LOAD.32 r0, [r10] LOAD.32 r0, [r10] FADD.32 r2,r1,r1 } } FADD.32 r3,r2,r2 from use of r0 FADD.32 r4,r3,r3 wait(load) { wai
Slide 22: Bifrost features
Bifrost features Leverages Mali’s scalable architecture Scalable to 32 shader cores 20% Scalable to 32 Higher energy Shader cores Major shader core redesign efficiency* New scalar, clause-based ISA New quad-based arithmetic units New geometry data flow Reduces memory bandwidth and foot
Slide 23: Tiler changes
Tiler changes Bifrost uses the same underlying hierarchical binning design as Midgard Significantly redesigned tiler memory structures Minimum buffer allocations eliminated Buffer allocation granularity now finer Micro-triangle elimination reduces the number of primitives stored in bin buf
Slide 24: Index-driven position shading
Index-driven position shading ½x Read/write bandwidth Tiler Position Tiler Varying Fragment [x times of storage size] Assembly Shading Culling Shading Shading 1x 1x ½x ½x ½x Processing Memory 3.5x 2.0x 2.5x 1.5x Positions Attribs Positions Attributes Trans- Polygon Vertex Vertex Indices Positions fo
Slide 25: Index-driven position shading
Index-driven position shading • Leverages existing coherency flows Driver • Multiple shader cores write Up to 32 shader cores supported Software transformed positions into a shared memory fifo. Shader Shader Shader Shader Job Manager Core 0 Core 1 Core 2 Core 31 • The fixed function Tiler reads the
Slide 26: Bifrost features
Bifrost features Leverages Mali’s scalable architecture Scalable to 32 shader cores 20% Scalable to 32 Higher energy Shader cores Major shader core redesign efficiency* New scalar, clause-based ISA New quad-based arithmetic units New geometry data flow Reduces memory bandwidth and foot
Slide 27: Memory system
Memory system Driver Software Shader Shader Shader Shader Job Manager Core 0 Core 1 Core 2 Core 31 Control Fabric L2 Cache L2 Cache L2 Cache L2 Cache Tiler MMU Segment Segment Segment Segment ACE Memory Bus ACE Memory Bus ACE Memory Bus ACE Memory Bus Full coherency using AMBA ACE protocol 27 © ARM2
Slide 28: Memory system
Memory system Full system coherency support Cortex-A73 Mali-G71 Supports tightly coupled CPU+GPU use cases CPU GPU L2 cache improvements Single logical L2 cache makes software easier CoreLink CCI-550 Fewer partial lines written to memory which improves LPDDR4 performance DMC-500 Supports
Slide 29: Next-generation heterogeneous computing
Next-generation heterogeneous computing Workload balancing – OpenCL 2.0 Introduces Shared Virtual memory overhead reduction 1 Memory 0.8 Mali-G71 goes one step further with fine -81% -90% grained buffers Normalized runtime 0.6 Initialization and processing Significantly eases development and 0
Slide 30: Summary
Summary Leverages Mali’s scalable architecture Scalable to 32 shader cores 20% Scalable to 32 Higher energy Shader cores Major shader core redesign efficiency* New scalar, clause-based ISA New quad-based arithmetic units New geometry data flow Reduces memory bandwidth and footprint 40%
Slide 31: Thank you!
Thank you! The trademarks featured in this presentation are registered and/or unregistered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. All other marks featured may be trademarks of their respective owners. Copyright © 2016 ARM Limited