ARM Holdings PLC · NASDAQ:ARM
ARM — Investor Presentation (March 2026)
29 slides from ARM's investor presentation, March 2026
Slide 1: World's most efficient agentic CPU
Wo r l d ’s m o s t e f f i c i e n t a g e n t i c C P U Performance Scale Efficiency 1
Slide 2: VT
VT
Slide 3: I/O for composable AI systems
I/O for composable AI systems Responsive performance 96x lanes PCIe Gen6 CXL 3.0 – memory expansion and more Up to 136 Arm Neoverse V3 cores AMBA CHI extension links Dedicated 2MB L2 cache per core Up to 3.7Ghz frequency World class Arm efficiency Incredible 3nm efficiency Maximum compute density 30
Slide 4: Maximum performance, density & efficiency
Air cooled Liquid cooled 36kW open rack V3 200kW open rack wide 30x 2 node 1U servers 42x 8 node 1U servers 8,160 performant CPU cores 45,696 performant CPU cores 180TB+ low latency memory 1PB+ low latency memory Maximum performance, density & efficiency 4
Slide 5: Contributions across the full stack
Contributions across the full stack Platform foundation Security & access Validation & tooling
Slide 6: Available now
arm AGI CPU Available now Q Quanta Computer Gas SAMSUNG micron.
Slide 7: Arm Neoverse compute platform
Linux/OS Cloud Native SaaS & Enterprise AI/ML (Open Source & Commercial) (Open Source & Commercial) … … … … Arm Neoverse compute platform
Slide 8: 1.25 Billion+ cores shipped
Google Container Actions Optimized OS 1.25 Billion+ VERACRUZ cores shipped 2019 2026
Slide 9: Paul Saab, Meta
Paul Saab OO Meta
Slide 10: The agentic data center
The agentic data center Cloud Agents CPU CPU CPU CPU CPU CPU CPU CPU AI data center CPU orchestrates Accelerators generate tokens Answer AI agent CPU CPU CPU CPU CPU ACCELERATOR ACCELERATOR CPU CPU CPU CPU CPU ACCELERATOR ACCELERATOR
Slide 11: The agentic data center
The agentic data center Cloud Agents CPU CPU CPU CPU CPU CPU CPU CPU AI data center CPU orchestrates Accelerators generate tokens Answer AI agent CPU CPU CPU CPU CPU ACCELERATOR ACCELERATOR CPU CPU CPU CPU CPU ACCELERATOR ACCELERATOR
Slide 12: The agentic data center
The agentic data center Cloud Agents CPU CPU CPU CPU CPU CPU CPU CPU AI data center CPU orchestrates Accelerators generate tokens AI agent CPU CPU CPU CPU CPU ACCELERATOR ACCELERATOR CPU CPU CPU CPU CPU ACCELERATOR ACCELERATOR
Slide 13: Partner logos
Gerebras cLou fa 5) OQ Meta ‘e r an OpenAl PO/ITRON rebelLtons_ SAP SK Ztecom
Slide 14: x86 CPU
x86 CPU High performance cores Execution overhead World class efficiency Legacy feature support Low latency design Modularity over latency Performance scales. Power stays predictable. Performance throttled. Technical debt.
Slide 15: Optimizing performance, scale, and efficiency
Optimizing performance, scale, and efficiency Efficiency Purpose-built, no legacy overhead No wasted energy or silicon Scale Linear scaling across cores Memory and I/O keep pace Performance More work per cycle Full performance, always x86 CPU Based on estimates.
Slide 16: Performance. Scale. Efficiency.
Performance. Scale. Efficiency. Sustained performance / Thread Sustained threads / Rack Performance / Watt 2.5 2.5 2.5 2 2 2 1.5 1.5 1.5 1 1 1 .5 .5 .5 0 0 0 x86 SMT-disabled Based on estimates.
Slide 17: Performance. Scale. Efficiency.
Performance. Scale. Efficiency. Sustained performance / Thread Sustained threads / Rack Performance / Watt 2.5 2.5 2.5 2 2 2 1.5 1.5 1.5 1 1 1 .5 .5 .5 0 0 0 x86 SMT-disabled x86 SMT-enabled Based on estimates.
Slide 18: World's most efficient agentic CPU
Wo r l d ’s m o s t e f f i c i e n t a g e n t i c C P U Performance Scale Efficiency 18
Slide 19: More than 2x performance per rack on Arm
More than 2x performance per rack on Arm Arm AGI CPU 36kW rack 30x 1U servers VS x86 CPU 8,160 CPU cores 36kW rack 17x 2U servers 4,352 CPU cores Based on estimates. 19
Slide 20: 2x performance per rack delivers up to $10B CAPEX savings
More than 2x performance per rack delivers Up to $10B CAPEX savings vs x86 CPU 1GW capacity Based on estimates.
Slide 21: Committed to future products
Committed to future products 3 2 Best in class performance, scale & Silicon efficiency Neoverse IP + CSS CSS V5 CSS V4 CSS V3 Now 2027 Future Timelines depict silicon sample availability.
Slide 22: IP + Compute Subsystems (CSS)
CPU GPU CPU GPU NPU NPU SYSTEM IP SYSTEM IP IP + Compute Subsystems (CSS)
Slide 23: ~$3B TAM
CPU ~$3B TAM GPU CPU GPU NPU NPU SYSTEM IP SYSTEM IP IP + Compute Subsystems (CSS) Based on estimates.
Slide 24: IP + CSS + First production silicon chip
CPU GPU CPU GPU NPU NPU SYSTEM IP SYSTEM IP IP + Compute Subsystems (CSS) + First production silicon chip 24
Slide 25: >$100B TAM
CPU >$100B TAM GPU CPU GPU NPU NPU SYSTEM IP SYSTEM IP By 2030 IP + Compute Subsystems (CSS) + First production silicon chip Based on estimates.
Slide 26: IP + CSS + First production silicon chip
CPU GPU CPU NPU GPU SYSTEM IP NPU SYSTEM IP IP + Compute Subsystems (CSS) + First production silicon chip
Slide 27: >$1T TAM
We are not stopping here CPU GPU CPU NPU SYSTEM IP GPU >$1T TAM SYSTEM IP NPU IP + Compute Subsystems (CSS) + First production silicon chip By 2030 Based on estimates.
Slide 28: Partner logos
ADVANTEST. altera ax ami O@ykcor, ARISTA #X ASE HOLDINGS MSRock aws @sBroapcom = cadence’ Canonical Grebras sults es ciouvriane — GAatabricks intel — @® = Furiosk# GitHub Google tussingrace foundry || marvenw services 0 Meta micron. BE Microsoft @MongopB <GinviplA = NX@ OpendAl ORACLE PO/ITRON Q reb
Slide 29: Arm trademarks notice
The Arm trademarks featured in this presentation are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. All other marks featured may be trademarks of their respective owners. www.arm.com/company/policies/trademarks