Slide 1: Drive and Layout Requirements for Fast Switching High Voltage MOSFETs
Drive and Layout Requirements for Fast Switching High Voltage MOSFETs
Slide 2: Contents
Contents • Introduction • Super-Junction Technologies • Influence of Circuit Parameters on Switching Characteristics – Gate Resistance – Clamp diodes – Ferrite Bead – Drive IC – External Cgd – Source Inductance • Practical Layout Requirements • Summary 2
Slide 3: E-Field Distribution of SJ Technology
E-Field Distribution of SJ Technology SJ Technology Allows Twice BV for Same Doping • Planar MOSFET • Super-Junction MOSFET E-Field E-Field BV A A A + - + - A + - + + + + + + + + + + - + - + - + BV + + + + + + + + + - + - + - + + - + - + - + + + + + + + + + + - + - + - + + - + - + - + + + + + + + +
Slide 4: Silicon Limit of HV MOSFETs?
Silicon Limit of HV MOSFETs ? • Planar MOSFET 9 Ron, sp 6 10 BV 2.5 E-FieldBV 60 A A 55 • A near linear relation between + + + + + + + + 50 Rds(on) and Breakdown Voltage + + + + + + + + Specific Rdson [mohm-cm2] 45 • A significant reduction of + + + + + + + + 40 conduction and switching losses +
Slide 5: Non-linear Coss in SJ MOSFET
Non-linear Coss in SJ MOSFET o r A C d a b c • Coss curve of super-junction MOSFET is highly non-linear 10000 Extremely fast dv/dt and di/dt and voltage and current oscillation SJ MOSFET Planar MOSFET 50ns/div 1000 Vgs : 5V/div Coss [pF] 100 Id:2A/div Vds:100V/div a b c 0.1 1 10 100 Vds [V]
Slide 6: SuperFET3 vs SuperFET2
SuperFET3 vs SuperFET2 SuperFET 3 SuperFET 2 DUTs FCH040N65S3 FCH041N60E BVDSS @ TJ=25℃ 650 V 600 V ID@ TC=25℃ 68.0A 77.0 A RDS(ON) max. ID=34A 40mΩ 41mΩ VGS(th) 2.5V ~ 4.5V 2.5V ~ 3.5V VGSS @ DC ±30V ±20V *Qg @ Vdd=400V, ID=34A, Vgs=10V * 158 nC -52% * 330 nC *Rg @ f = 1 MHz * 0.7 Ω 1.2 Ω *EOSS @ 4
Slide 7: SuperFET3 - Low Gate Charge and Input Capacitance
Gate Charge Characteristic SuperFET3 - Low Gate Charge and Input Capacitance 12 30000 SuperFET3 SuperFET2 25000 SuperFET 3 SuperFET 2 10 20000 8 Vgs [V] 15000 6 Ciss [pF] 4 10000 2 Ciss = Cgs + Cgd (Cds = shorted) ※ Notes : 0 1. VGS = 0 V 0 50 100 150 200 250 300 350 2. f = 1 MHz Gate Charge [nC] 50
Slide 8: Clamped Inductive Switching Circuit & Waveforms and Loss Definition
Clamped Inductive Switching Circuit & Waveforms and Loss Definition • Test Circuit which is used for the following measurements. 8
Slide 9: Effects of Gate Resistance at Turn On Transient
Effects of Gate Resistance at Turn On Transient 30 12000 Rg=3.3ohm Rg=6.8ohm 10000 Rg=10ohm 20 Rg=27ohm Gate-Source Voltage [V] Rg=47ohm 8000 Rg=3.3ohm 10 6000 Rg=6.8ohm Pon [W] Rg=10ohm 4000 Rg=27ohm Rg=47ohm 0 2000 0 -10 -2000 -100 -80 -60 -40 -20 0 20 40 -100 -80 -60 -40 -20 0 20 40 Time [ns] Tim
Slide 10: Effects of Gate Resistance at Turn Off Transient
Effects of Gate Resistance at Turn Off Transient 20 Rg=3.3ohm 6000 Rg=6.8ohm Rg=10ohm 5000 Rg=27ohm Gate-Source Voltage [V] 10 Rg=47ohm 4000 Rg=3.3ohm Rg=6.8ohm Poff [W] 3000 Rg=10ohm Rg=27ohm 2000 Rg=47ohm 0 1000 0 -10 -1000 -100 -80 -60 -40 -20 0 20 40 60 -100 -80 -60 -40 -20 0 20 40 60 Time [ns]
Slide 11: Effects of Gate Resistance
Effects of Gate Resistance Eon& Eoff @ Id=9A, Vds=380V 120 Eon 110 Eoff 100 90 80 Eon[uJ] 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 Rg, Gate Resistor [ohm] • Critical control parameter in gate-drive design is external series gate resistor (Rg). • From an application standpoint, selecting the opt
Slide 12: Reverse Recovery Effect
Reverse Recovery Effect Si Diode vs SiC Schottky Diode 10 6A SiC Schottky diode 8 8A Si diode 6 4 Current [A] 2 0 -2 -4 -6 -80.0n -60.0n -40.0n -20.0n 0.0 20.0n 40.0n 60.0n 80.0n 100.0n Time[s] 12
Slide 13: Effect of Clamp Diodes at Turn On
Effect of Clamp Diodes at Turn On Si Diode vs SiC Schottky Diode IF : 2A/div. Vds : 100V/div. Eon=50.72uJ Vr: 100V/div. Id : 2A/div. Time : 20ns/div. Diode & MOSFET waveforms @ Turn-on with SiC Schottky diode Eon=90.33uJ Diode & MOSFET waveforms @ Turn-on with Si diode 13
Slide 14: Effect of Clamp Diodes at Turn Off
Effect of Clamp Diodes at Turn Off Si Diode vs SiC Schottky Diode Vgs : 5V/div. Eoff Id : 0.5A/div. 6A SiC SBD 6A SiC diode Vds : 100V/div. 8A Si Diode Time : 100ns/div. Turn off @ Id=1A, Rg=4.7 Ω with 6A SiC SBD (Ref : 8A Si Diode) 8A Si Diode 14
Slide 15: Effect of Clamp Diodes
Effect of Clamp Diodes Si Diode vs SiC Schottky Diode MOSFET Eon @ Id=9A, Vdd=380V 80 100 With Si Diode With Si Diode With SiC Schottky 70 With SiC Schottky Diode 60 80 50 dv/dt [V/ns] Eon[uJ] 60 40 30 40 20 10 20 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 Rg, Gate Resistor [ohm] Rg [ohm] • SiC S
Slide 16: Effects of Ferrite Bead
Effects of Ferrite Bead Vgs without ferrite bead Vgs without ferrite bead Vgs with ferrite bead Vgs : 10V/div. Vgs : 10V/div. Vgs with ferrite bead Time :10ns/div. (a) Vgs at Turn-on Transient (b) Vgs at Turn-off Transient 16
Slide 17: Equivalent Circuit of Ferrite Bead
Equivalent Circuit of Ferrite Bead Z R Gate Ferrite Bead X Cpara Rbead Lbead Rpara Z R jX 17
Slide 18: Effects of Current Capability of Driver IC
Effects of Current Capability of Driver IC TABLE I. Comparisons of Critical Specification of Gate Drivers DEVICE CONDITION IPK_SINK IPK_SOURCE FAN3122T CLOAD=1.0uF,f=1kHz,Vdd=12V 11.4[A] -10.6[A] FAN3224T CLOAD=1.0uF,f=1kHz,Vdd=12V 5.0[A] -5.0[A] FAN3111C CLOAD=1.0uF,f=1kHz,Vdd=12V 1.4[A] -1.4[A] *
Slide 19: Effects of Gate Drive Circuit
Effects of Gate Drive Circuit Vcc Don Ron Don Ron Vcc OUT Roff OUT Qoff Doff Roff GND GND • PNP Tr turn-off can reduce gate ringing. • It’s possible to reduce parasitic components in PCB. * Ron=10hom, Roff=4.7ohm • Keep loop area as small as possible to avoid worse EMI and switching behavior. 19
Slide 20: Measurement Technique
Measurement Technique Probe R L C C Oscilloscope R L Ground Lead Probes are circuits composed of distributed R,L, and C for AC signals. A total probe impedance varies with switching frequency. Standard gate probing Ringing R1 CP RP RL 8pF 10M LG The probe ground lead adds inductance to the circuit
Slide 21: Keep the Loop Probe Small!
Keep the Loop Probe Small! • Measurement with standard setup 15 Measuremet with standard setup Measuremet with Probe tip S D G 10 Vgspk-pk=26V 5 Vgs [V] 0 Vgspk-pk=11.2V -5 • Measurement with Probe Tip -10 S D G -15 -100 -80 -60 -40 -20 0 20 40 60 80 100 Time [ns] 21
Slide 22: Package and Layout Parasitics
Package and Layout Parasitics Package parasitics 1cm / 0.25mm trace (L/W) ≈ 6-10nH L=10nH, di/dt=500A/μs Vind=5V L=10nH, di/dt=1,000A/μs Vind=10V Layout parasitics A lot of layout parasitic has to be considered! 22
Slide 23: MOSFET Oscillation Circuit
MOSFET Oscillation Circuit Dboost MOSFET Resonant circuit LD L LD given by external Cgd_ext. coupling Cgd_ext. Osc illation circuit given by external capacitance C LD1 GD couple capacitance Ld1 Rg Cgd_int. CO CDS MOSFET RG-ext. =5.1O LG Lg1 Rg_int. Cds LG1 LG CGS R LOAD LS1 Cgs Ls1 Resonant circuit
Slide 24: Layout Capacitance Example with High External CGD
Layout Capacitance Example with High External CGD x A x y y Capacity between trace pitches 0 r A d C d External CGD External CGD too high!! Drain Gate Drain Gate External CGD External CGD External CGD (a) Single layer PCB (b) Double layer PCB 24
Slide 25: Layout Capacitance Examples with Reduced External CGD
Layout Capacitance Examples with Reduced External CGD Gate Drain External CGD Drain Gate Gnd-plane or Shield- External CGD plane reduces CGD Minimized external CGD Minimized external CGD (a) double layer PCB Both solutions allow use of SJ Devices (b) multi layer PCB 25
Slide 26: Layout Example Large External CGD
Layout Example Large External CGD Vgs Shows Higher Spikes During Turn Off PCB example with large external CGD Gate Coupling area VDS VGS Drain DVGS ~ 18V 26
Slide 27: Layout Example Small External CGD
Layout Example Small External CGD Vgs Shows Lower Spikes During Turn Off PCB example with small external CGD Coupling area VDS Drain Gate VGS DVGS ~ 4V 27
Slide 28: Turn-off Gate Oscillation Mechanism
Turn-off Gate Oscillation Mechanism VDS+ During T2 SJ MOSFET LD Id 10000 Coss [pF] VGS_int+ VGS+ 1000 RG LG LG_int VGS_int - 100 LS_int Discharging 0.1 1 10 100 - Vds [V] dI D LS VLS LS dt + Id Negative di/dt VGS- VDS- t VGS : 5V/div • Keep the commutation loop as small as possible! • Minimize
Slide 29: Effects of Source Inductance
Effects of Source Inductance LS=1n and 10nH Vgs Vgs (a) Vgs waveform for low LS (b) Vgs waveform for High LS Vds Id * Topology : 500W Interleaved CRM PFC * MOSFET : FCPF13N60N * Diode : FFPF20UP60DN * Gate Resistor : Ron=51ohm, Roff=10ohm (c) Vds and Id waveform 29
Slide 30: Gate oscillation vs Package
Gate oscillation vs Package Through hole vs SMD vs Kelvin source SMD ID=8A 600V/199mΩ, Power88 600V/199mΩ, D2PAK 600V/199mΩ, TO220 Kelvin Source SMD SMD Through hole Turn-off Transient Gate Oscillation Gate Oscillation 30
Slide 31: Design Tips - Practical Layout Example - Boost PFC
Design Tips - Practical Layout Example – Boost PFC Bad Layout: Good Layout: Driver and gate resistor far away Connect the driver-stage Gnd Driver & Rg as close as Increased external directly to the source pin to possible to the gate pin of from gate pin of MOSFET G-D capacitance achieve best perform
Slide 32: Design Tips - Practical Layout Example - Paralleling MOSFETs
Design Tips - Practical Layout Example - Paralleling MOSFETs Minimized source inductance to reference point for gate drive minimized Two independent totem pole drivers very close to MOSFET gate Minimized Cgd: Gate and Drain trace at 90° angle 32
Slide 33: Summary
Summary How to Use Super-Junction MOSFET in Practical Layouts • To achieve the best performance of Super-Junction MOSFETs, optimized layout is required • Gate driver and Rg must be placed as close as possible to the MOSFET gate pin • Separate POWER GND and GATE Driver GND • Minimize parasitic Cgd ca
Slide 34: ON Semiconductor
ON Semiconductor® 34 ON Semiconductor® On