Slide 1: Intro to Memory Packaging
Intro to Memory Packaging Reviewed 2025 © 2024-2025 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Statements regarding products, including
Slide 2: Copyright guidelines
Copyright guidelines By using any content provided by the Micron Educator Hub, you acknowledge that Micron Technology, Inc. (“Micron”) is the sole owner of the content and agree that any use of the content provided by the Micron Educator Hub must comply with applicable laws and require strict compli
Slide 3: How to cite sources from the Micron Educator Hub
How to cite sources from the Micron Educator Hub • Micron is committed to collaborate with Use case How to cite sources educators to make semiconductor memory education resources available through the a) Whole slide deck or whole No additional citation required document Micron Educator Hub Descripti
Slide 4: Table of Contents
Table of Contents 1 Goal, Objectives and Target Audience 2 Introduction to Packaging 3 Diverse Ecosystem and Knowledge Base for a Successful Packaging Team 4 Purpose of Packaging 5 Scaling Challenges in Packaging 6 Thermal Simulations in Packaging 7 Lab Testing in Packaging 8 Glossary and Key Termin
Slide 5: Introduction to Packaging - Goal and Objectives
Introduction to Packaging - Goal and Objectives Participants will learn the role packaging plays in semiconductor manufacturing, the diverse ecosystem and knowledge base required for a successful packaging team, and industry trends in packaging. Objectives: 1. Describe the different types of packagi
Slide 6: Target Audience
Target Audience • This Introduction to Packaging module covers the basics of Pro tip Semiconductor packaging. Everyone interviewing at Micron can • Interns, NCGs (New College Grads), and new employees in technical use this presentation to prepare for roles need to understand these concepts the inter
Slide 7: Introduction to Memory Packaging
Introduction to Memory Packaging 7
Slide 8: Introduction to Packaging
Introduction to Packaging The semiconductor package is the components surrounding a memory die that enables its use in circuitry. Package Silicon Die Circuit Board 8
Slide 9: Semiconductor Memory Manufacturing Flow
Semiconductor Memory Manufacturing Flow Start Material: Silicon is purified and formed into wafers (outside Micron). Wafer-Level Fabrication: Electronic devices (transistors, resistors, capacitors, etc.) are fabricated on the silicon wafers, and are then interconnected together into complete circuit
Slide 10: What goes into making Semiconductor Packages?
What goes into making Semiconductor Packages? Silicon integrated circuits Metal plated contacts Underfill mold compounds Mechanical and epoxies Chemistry Engineering Bonding physics and Materials Electrical Science Engineering chemistry Solder bumps 10
Slide 11: Additional Tasks
Additional Tasks Mechanical Process Gases Materials fixturing Very diverse ecosystem and Testing Chemical equipment Fine chemicals delivery systems knowledge base to develop and deploy semiconductor packaging! Grinding and removing Dicing Plasma etching materials And more…! 11
Slide 12: Engineering Disciplines in Packaging
Engineering Disciplines in Packaging Tackling challenges in packaging requires a diverse educational background • Mechanical Engineering: Evaluate package warpage, mechanical integrity, thermal characterization. • Electrical Engineering: Design and evaluate electrical routing of die and interposers
Slide 13: Introduction to Packaging
Introduction to Packaging A) Silicon Die C) Secondary (die-to-package) Interconnects E) Heat Dissipation • Semiconductor Memory • Wire bonds, bumps, or pillars • Heat sinks/spreaders • Thermal Interface Materials B) Interposer D) Primary (package-to-board) Interconnects F) Environmental Protection •
Slide 14: Purpose of Packaging
Purpose of Packaging 1. Electrical interface between the chip and outer circuitry: • Can “adapt” between the different scale size of metal connections on the die to wires on circuit. • Improves the quality of signal transmission. Silicon Die Die-to-Package connections, μm scale Silicon Interposer Pa
Slide 15: Purpose of Packaging
Purpose of Packaging 2. Physical protection of die: • Thinly diced silicon die are fragile and susceptible to mechanical stresses and environmental contamination. Encapsulation can be made of Silicon Die epoxy, metal, plastic, etc. Silicon Interposer Plastic Encapsulation: Injection molding process
Slide 16: Purpose of Packaging
Purpose of Packaging 3. Heat dissipation: • Complex integrated circuits produce a lot of heat that can burn up a die without the heat dissipation of the package. Thermal Interface Material Silicon Die Thermally conductive encapsulation or metal lid Silicon Interposer Thermally Conductive Fillers: Th
Slide 17: Purpose of Packaging
Purpose of Packaging 4. Expand functionality: • Stack die to multiply the available memory. • Increase functionality by including logic or different types of memory. Multi-die Package Hybrid Memory Silicon Die Silicon Die Logic Layer 17
Slide 18: Purpose of Packaging
Purpose of Packaging 5. Customer ease of use: • Standardized sockets allow for quick attachment, replacement, or upgrade of products. Encapsulated Die Package Standardized layout of package-to- Silicon Interposer board interconnects Industry standardized “socket” layout Customer Motherboard 18
Slide 19: Introduction to Packaging
Introduction to Packaging In the process of fabricating die, chemical and laser etchings expose connections on the top of die. To make an electrical connection, wires can be bonded to these connections on the top, or the die can be inverted (“flipped”) to apply bonds to the bottom. Wire bond: Very t
Slide 20: Wire bonded Package
Wire bonded Package Utilize wires bonded to pads on the top of the die down to pads on the substrate. • Cheaper, easier fabrication process. • Adaptable to different chip sizes and other package design considerations. • Requires a larger overall package. • Long wires result in greater parasitic volt
Slide 21: Bumped Package
Bumped Package Solder ball “bumps” make electrical connections between metal pads on bonding surfaces. • More complex fabrication process, increased cost compared to wire bonds. • Changes to chip size and other package designs often require re-designing the bonding pattern. • Small electrical connec
Slide 22: Package-on-Package
Package-on-Package “Bumped” die are not easily stacked. Can expand memory then by stacking entire packages. Enables blended bonding types as well. Die stacked using wire bonds Package 1 Metal Traces Package 2 Inter-Package Vias Encapsulation omitted for clarity 22
Slide 23: Through Silicon Vias (TSV’s)
Through Silicon Vias (TSV’s) Newer fabrication technique runs metal pillars or “vias” through the thickness of the die. Electrically connects the die and bonds to the interposer. Cross Sectional Diagram Bond pad TSV Pillar Underfill Interposer Vias 23
Slide 24: Challenges in Packaging: Scaling!
Challenges in Packaging: Scaling! 10000 HBM Acronyms DIP Dual Inline Package FP Flat Package HMC BGA Ball Grid Array CSP Chip Scale Package Package Interconnect Density PoP Package on Package 1000 PiP Package in Package RDL Redistribution Layer SiP eMMC Embedded Multimedia Card F2F Face to Face SiP
Slide 25: Thermal Simulation
Thermal Simulation Thermal modeling is a powerful tool for predicting how packages will perform while in different situations. 25
Slide 26: Laboratory Testing
Laboratory Testing Computer simulations require comparison to experimental data for validation. Four locations Heat Source Power (P) In Cu blocks T1 d12 Cu Q 𝒅𝟐 T2 𝑻𝑻 = 𝑻𝟐 − (𝑻 − 𝑻𝟐) d2 𝒅𝟏𝟐 𝟏 Sample Insulators Sample 𝒅𝟑 d3 Sample 𝑻𝑩 = 𝑻𝟑 + (𝑻 − 𝑻𝟒) T3 𝒅𝟑𝟒 𝟑 d34 Cu T4…
Slide 27: Laboratory Testing Environments
Laboratory Testing Environments Test die mounted to board. Cold plate (20 C). Test die mounted to board. Die Conducts heat away is in contact with cold plate. from die. Wire connections to heat the die, and to detect temperature. Wire connections to heat the die, and to detect temperature. Acrylic c
Slide 28: Key Terminology Glossary
Key Terminology Glossary Micron
Slide 29: Glossary
Glossary Term or acronym Definition/description BGA Ball Grid Array. Package type that utilizes an array of solder balls for electrical connection. Bumped Package A package that uses solder ball "bumps" to make electrical connections between metal pads on bonding surfaces. CSP Chip Scale Package. Pa
Slide 30: Glossary
Glossary Term or acronym Definition/description PiP Package in Package. Two or more intermediate substrates, with die stacks on each, stacked and encapsulated into a single package PoP Package on Package. A method of stacking entire packages to expand memory. Two or more completed packages that are
Slide 31: Document Updates
Document Updates 31
Slide 32: Document Updates
Document Updates Date Description January • Added goals and objectives (slide 5) 2025 • Added target audience (slide 6) • Added semiconductor memory manufacturing flow (slide 9) • Added several new images • Added acronym legends • Added glossary section (slide 28-30) 32
Slide 33: © 2024–2025 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject
© 2024–2025 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Statements regarding products, including statements regarding product features,