Slide 1: Introduction to Fabrication
Introduction to Fabrication Reviewed 2025 © 2020-2025 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Statements regarding products, includi
Slide 2: Copyright guidelines
Copyright guidelines By using any content provided by the Micron Educator Hub, you acknowledge that Micron Technology, Inc. (“Micron”) is the sole owner of the content and agree that any use of the content provided by the Micron Educator Hub must comply with applicable laws and require strict compli
Slide 3: How to cite sources from the Micron Educator Hub
How to cite sources from the Micron Educator Hub • Micron is committed to collaborate with Use case How to cite sources educators to make semiconductor memory education resources available through the a) Whole slide deck or whole No additional citation required document Micron Educator Hub Descripti
Slide 4: Table of Contents
Table of Contents 1 Goals, Objectives and Target Audience 2 Introduction to Fabrication 3 Basic CMOS Process Flow (Traveler) 4 Glossary 5 Document Updates 4
Slide 5: Introduction to Fabrication - Goal and Objectives
Introduction to Fabrication - Goal and Objectives In this introductory course participants will learn the basics of semiconductor fabrication at the wafer level. Objectives: 1. Become familiar with general terms used in semiconductor manufacturing 2. Understand the purpose of the ten different fab a
Slide 6: Target Audience
Target Audience • This Introduction to Fabrication module covers the basics of Pro tip semiconductor fabrication at the wafer level. Everyone interviewing at Micron can • Interns, NCGs (New College Grads), and new employees in technical use this presentation to prepare for roles need to understand t
Slide 7: Introduction to Fabrication
Introduction to Fabrication 7
Slide 8: Fabrication
Fabrication Fabrication is the process of building circuits on a silicon wafer in a cleanroom environment where all aspects of production (temperature, power, chemistries, moisture, contamination, etc.) are tightly controlled. Fabrication (a.k.a. Manufacturing) Silicon wafers are purchased How long
Slide 9: Semiconductor manufacturing is done in cleanrooms
Semiconductor manufacturing is done in cleanrooms View of a fab cleanroom from the ceiling, on the path of the AMHS (Automated Material Handling System) 9
Slide 10: There are hundreds of tools/equipment in a semiconductor fab
There are hundreds of tools/equipment in a semiconductor fab View of a tool in a fab cleanroom 10
Slide 11: Automation inside a tool
Automation inside a tool Picture inside an equipment tool: robot that handles wafers 11
Slide 12: Cleanrooms & Classification Standards
Cleanrooms & Classification Standards Q: What Is a Cleanroom? A: It is a room that has HEPA (High Efficiency Particulate Air) filtration to remove particles from the air. Cleanrooms are used for manufacturing where high levels of cleanliness and sterility are required. Common applications of the cle
Slide 13: Semiconductor Memory Manufacturing Flow
Semiconductor Memory Manufacturing Flow Start Material: Silicon is purified and formed into wafers (outside Micron). This document Wafer-Level Fabrication: Electronic devices (transistors, resistors, focuses on this capacitors, etc.) are fabricated on the silicon wafers, and are then part interconne
Slide 14: Construction Analogy
Construction Analogy • The wafer fabrication process is similar to the construction of a building, except on a MUCH smaller scale. • We start out with plans or designs and then build the foundation followed by many interconnecting layers (or floors). 10’s of meters Billionths of meters (nanometers)
Slide 15: Wafer Processing Areas – Five Basic Actions
Wafer Processing Areas – Five Basic Actions Add Material Remove/Etch Create Patterns Change Electrical Measure/Inspect Material Properties Dopants Resist Resist Oxide Oxide Oxide Oxide Oxide Silicon Silicon Silicon Silicon Silicon • Diffusion • Dry Etch • Photolithography • Implant • Metrology • CVD
Slide 16: Simplified Wafer Processing Flow
Simplified Wafer Processing Flow Wet Wafer Start Probe Process End of Fabrication Beginning of Fabrication Clean FILMs Wet Wet Ion CVD, Diffusion, PVD CMP Process Process Implant Deposition, Oxidation, Clean Metallization, Anneal, or Clean Planarization Plating (Wet) Photo Patterning Wet Process Dry
Slide 17: Simplified Wafer Processing Flow
Simplified Wafer Processing Flow Wet Wafer Start Probe Process End of Fabrication Beginning of Fabrication Clean FILMs Wet Wet Ion CVD, Diffusion, PVD CMP Process Process Implant Deposition, Oxidation, RDA RDA RDA Clean Metallization, Anneal, or Clean Planarization Plating (Wet) RDA Photo Patterning
Slide 18: Wafer Process Traveler and Recipes
Wafer Process Traveler and Recipes Step # Traveler Step Fab Area A Traveler is the sequential list of every step needed to make a memory chip. Years ago, it was 161 TG - GATE HARDMASK DEPOSITION CVD printed on cleanroom paper and “traveled” along 162 TG - GATE PHOTO PATTERN PHOTO with the box of waf
Slide 19: Breakout of Steps by Functional Area
Breakout of Steps by Functional Area • There are 10 primary “functional areas” of the fab: • CMP: Chemical Mechanical Planarization • CVD: Chemical Vapor Deposition • Diffusion • Dry Etch • Implant • Metrology • Photolithography (a.k.a. Photo) • PVD: Physical Vapor Deposition • RDA: Real time Defect
Slide 20: Zoom In to 3D Model
Zoom In to 3D Model • 3D models are used in this presentation to explain the fabrication process step by step • These two slides will help to orient the location and scale of the 3D models that are used to describe the traveler flow. One Memory Bank 5.0 mm Wafer Map Over 1000 die per wafer 7.5 mm On
Slide 21: Zoom In to 3D Model (continued)
Zoom In to 3D Model (continued) 3D Model of a Small Section of CMOS Periphery 1 Memory Array and Periphery 5 One Memory Bank Small section of Periphery 21
Slide 22: Photo Mask Levels
Photo Mask Levels ▪ During the fabrication process, patterns are created on the wafer using a series of photomasks. ▪ Each mask has a unique pattern ▪ A typical DRAM or NAND flow may have dozens of different masks ▪ Micron convention is to assign a 2-digit alphanumeric code to each mask. ▪ The table
Slide 23: Basic CMOS Process Flow (Traveler)
Basic CMOS Process Flow (Traveler) 23
Slide 24: Basic CMOS Traveler
Basic CMOS Traveler • In the next slides we will show a Step # Traveler Step Fab Area simplified traveler used to build 1 WAFER START SUPPORT CMOS transistors (NMOS and 2 PAD OXIDE GROWTH DIFFUSION PMOS transistors) along with 3 NITRIDE DEPOSIT DIFFUSION contacts and a metal routing layer. 4 NW N-WE
Slide 25: WAFER START with BARE SILICON SUBSTRATE
WAFER START with BARE SILICON SUBSTRATE • Double-side polished bare silicon wafers (with alignment “notch”), also called Silicon Substrates, are received from our external suppliers in 25-wafer Front- Opening Shipping Boxes (FOSB) Alignment Notch - Wafers are transferred into a Front-Opening Unified
Slide 26: …for the record… 300mm is the size of a record
…for the record… 300mm is the size of a record 26
Slide 27: PAD OXIDE GROWTH [DIFFUSION]
PAD OXIDE GROWTH [DIFFUSION] • In the Diffusion Area a thin film of silicon dioxide is grown on the surface of the wafer to protect the silicon substrate from surface damage during implants and to keep the surface clean and free from defects. • Silicon dioxide is usually referred as “oxide” and is a
Slide 28: Oxidation (Diffusion)
Oxidation (Diffusion) Photo and schematic of a Diffusion vertical furnace tube • The Diffusion area of the fab consists primarily of vertical furnace tubes where many wafers can be processed at a Outer tube time (a batch process – upwards of 125-wafers at a time) Inner liner • Different processes ta
Slide 29: NITRIDE DEPOSIT [DIFFUSION]
NITRIDE DEPOSIT [DIFFUSION] • In the Diffusion Area a thin film of silicon nitride (Si3N4) is deposited on top of the Pad Oxide. This silicon nitride film will be used later in the flow as a stop layer for a polishing process. • Silicon nitride is usually referred as “nitride” Detail Close-up Pad Ox
Slide 30: Circuit Elements with Human Hair
Circuit Elements with Human Hair This hair is ~60 μ wide. Hair may range 40-120 μ wide. Human Hair 30
Slide 31: Circuit Elements with Human Hair
Circuit Elements with Human Hair Human Hair This hair is ~60 μ wide. Hair may range 40-120 μ wide. 31
Slide 32: Circuit Elements with Human Hair
Circuit Elements with Human Hair Human Hair This hair is ~60 μ wide. Hair may range 40-120 μ wide. ~60um 32
Slide 33: NW N-WELL PHOTO PATTERN [PHOTO]
NW N-WELL PHOTO PATTERN [PHOTO] • In the Photolithography Area the “NW” reticle or mask is used to define a pattern in photoresist. The pattern will open certain areas where N-Wells are needed for the formation of PMOS transistor devices. • Metrology: – Resist Thickness: ~ very thick to block implan
Slide 34: Photolithography
Photolithography • The Photolithography area defines a temporary pattern that other areas (usually Dry Etch or Light Implant) use as a mask to create the structures needed on the wafer. Reticle (Mask) • The temporary pattern is created on a photosensitive film called photoresist (or resist). • Patte
Slide 35: Reticles
Reticles Light • Reticles, also called Masks, are used in the Photolithography scanner to expose a temporary pattern on the surface of the silicon wafer. Reticle (Mask) • The reticle is a quartz plate with a chrome and other layers deposited across one side, into which patterns are exposed and etche
Slide 36: NW N-WELL IMPLANT [IMPLANT]
NW N-WELL IMPLANT [IMPLANT] • In the Implant Area an ion implanter shoots phosphorous ions deep into the silicon to create an N-Well. The N-Well will provide the background doping needed to form PMOS transistors. The thick photoresist prevents the ions from entering the wafer in areas where N- Wells
Slide 37: Ion Implantation
Resist Ion Implantation Ion beam • Dopants are introduced into the silicon via a high-energy beam of ions that is directed at Implant the wafer surface. • The electrical properties of the silicon wafer Silicon are modified by “doping” with selected impurities. • The most common dopants are boron, ph
Slide 38: CMOS = Complimentary Metal Oxide Semiconductor Transistor
CMOS = Complimentary Metal Oxide Semiconductor Transistor 38
Slide 39: Before Anneal
Before Anneal CMOS = Complimentary Metal Oxide Semiconductor Transistor 39
Slide 40: After Anneal
After Anneal CMOS = Complimentary Metal Oxide Semiconductor Transistor 40
Slide 41: NW RESIST STRIP [WET PROCESS]
NW RESIST STRIP [WET PROCESS] • In the Wet Process Area plasma and wet chemistry are used to remove the photoresist after the implant is complete. • Metrology: – There should be no residual resist left on the wafer. Pad Oxide 41
Slide 42: Wet Process – Wafer Cleaning
Wet Process – Wafer Cleaning • The Wet Etch area uses chemical baths and de-ionized water to remove films and clean wafers to reduce defectivity. • After every patterning operation, one or more wet process steps are used to remove the leftover photoresist and clean up residual organics, particles, a
Slide 43: Wet Process – Wafer Cleaning
Wet Process – Wafer Cleaning • The Wet Etch area uses chemical baths and de-ionized water to remove films and clean wafers to reduce defectivity. • After every patterning operation, one or more wet process steps are used to remove the leftover photoresist and clean up residual organics, particles, a
Slide 44: Wet Process – Wafer Cleaning
Wet Process – Wafer Cleaning • The Wet Etch area uses chemical baths and de-ionized water to remove films and clean wafers to reduce defectivity. • After every patterning operation, one or more wet process steps are used to remove the leftover photoresist and clean up residual organics, particles, a
Slide 45: Wet Process – Wafer Cleaning
Wet Process – Wafer Cleaning • The Wet Etch area uses chemical baths and de-ionized water to remove films and clean wafers to reduce defectivity. • After every patterning operation, one or more wet process steps are used to remove the leftover photoresist and clean up residual organics, particles, a
Slide 46: Wet Process – Wafer Cleaning
Wet Process – Wafer Cleaning • The Wet Etch area uses chemical baths and de-ionized water to remove films and clean wafers to reduce defectivity. • After every patterning operation, one or more wet process steps are used to remove the leftover photoresist and clean up residual organics, particles, a
Slide 47: Wet Process – Wafer Cleaning
Wet Process – Wafer Cleaning • The Wet Etch area uses chemical baths and de-ionized water to remove films and clean wafers to reduce defectivity. • After every patterning operation, one or more wet process steps are used to remove the leftover photoresist and clean up residual organics, particles, a
Slide 48: PW P-WELL PHOTO PATTERN [PHOTO]
PW P-WELL PHOTO PATTERN [PHOTO] In the Photolithography Area the “PW” mask is used to define a pattern in photoresist. The pattern will open certain areas where P-Wells are needed for the formation of NMOS devices. Metrology: Resist Thickness: very thick to block implant Critical Dimension (
Slide 49: PW P-WELL IMPLANT [IMPLANT]
PW P-WELL IMPLANT [IMPLANT] • In the Implant Area an ion implanter shoots boron ions deep into the silicon to Q) What do you think create a P-Well. The P-Well will provide the background doping needed to is the next Traveler form NMOS transistors. The thick photoresist prevents the ions from enterin
Slide 50: PW RESIST STRIP [WET PROCESS]
PW RESIST STRIP [WET PROCESS] • In the Wet Process Area plasma and wet chemistry are used to remove the photoresist after the implant is complete. • Metrology: – There should be no residual resist left on the wafer. Silicon Nitride Pad Oxide 50
Slide 51: AA HARDMASK LAYERS DEPOSIT [CVD]
AA HARDMASK LAYERS DEPOSIT [CHEMICAL VAPOR DEPOSITION (CVD)] • In the CVD Area a thick film of carbon (C) is deposited followed by a thin silicon-based (Si) film. Together these films comprise a “hardmask” which allows us to etch very small features while keeping the photoresist layer as thin as pos
Slide 52: Chemical Vapor Deposition (CVD)
Chemical Vapor Deposition (CVD) • CVD is used to deposit a variety of insulating and conductive films at multiple places in the Traveler. • Gases are introduced into a chamber. A solid film, which is a product of the reaction, deposits on the wafer. • Most CVD processes also use plasma technology (s
Slide 53: AA ACTIVE AREAS PHOTO PATTERN [PHOTO]
AA ACTIVE AREAS PHOTO PATTERN [PHOTO] In the Photolithography Area the “AA” mask is used to define a pattern in photoresist. The pattern defines “active areas” where CMOS devices will be formed. Between the active areas, trenches will be etched into the silicon substrate to provide electrical isolat
Slide 54: Why Hardmask?
The Hardmask Approach Why Hardmask? Original Thick Resist Photoresist: Photo Perspective ☺ THICK Photoresist: Etch Perspective ☺ Remaining Hardmask: Etch Perspective ☺ Resist • Necessary to ensure resist is not completely Permanent • Thin resist for high resolution pattern eroded before the etch is
Slide 55: AA HARDMASK DRY ETCH [DRY ETCH]
AA HARDMASK DRY ETCH [DRY ETCH] • In the Dry Etch Area a plasma process is used to transfer the AA photoresist pattern into the underlying hardmask layers. The hardmask layers will provide a more robust mask for the subsequent trench etch than photoresist. • Notes: – This step is also known as “Dry
Slide 56: Dry Etch
Dry Etch • The Dry Etch area removes (etches) films using plasma (ionized gases). Dry Etch usually processes wafers after a temporary mask has been previously patterned, e.g. photoresist or a hardmask. The mask protects some regions of the wafer. Dry Etch only removes films from the unprotected regi
Slide 57: Dry Etch
Dry Etch Resist (and hardmask) thickness is engineered so there is still some left after the etch is complete to ensure the film underneath is protected. The etch step is usually followed by a “strip” step which removes the remaining resist or hardmask. Before After Plasma Generated Ions and Free Ra
Slide 58: AA STI DRY ETCH [DRY ETCH]
AA STI DRY ETCH [DRY ETCH] • In the Dry Etch Area a second plasma process is used to etch trenches into Q) What do you think the silicon wafer. For this process, the mask is the Si hardmask and the is the next Traveler carbon hardmask. These trenches will be filled with oxide and will provide step?
Slide 59: AA RESIST STRIP [WET PROCESS]
AA RESIST STRIP [WET PROCESS] • In the Wet Process Area plasma and wet chemistry are used to remove the remaining carbon hardmask after the trench etch is complete. (similar recipe used to remove photoresist) • Metrology: – There should be no residual carbon left on the wafer. Detail Close-up Pad Ox
Slide 60: Metrology
Metrology • The Metrology area takes measurements that evaluate the results of process operations. • Examples of measurements are film thicknesses, critical dimensions or CDs (e.g., line width, line space, contact diameter, etc.), lithography overlay, film resistivity, surface planarity, film compos
Slide 61: Real-Time Defect Analysis (RDA)
Real-Time Defect Analysis (RDA) • The Real-Time Defect Analysis (RDA) area inspects wafers Physical defects for defects at critical points in the manufacturing process. • The RDA area monitors in-line wafers and provides critical data collection and analysis services to fab process areas • The proce
Slide 62: AA STI OXIDE DEPOSIT [CVD]
AA STI OXIDE DEPOSIT [CVD] • In the CVD Area a thick film of silicon dioxide is deposited to fill the trenches. Q) What do you think Only the oxide in the trenches is needed, so the unwanted surface oxide will is the next Traveler be removed in the next Traveler step. step? Metrology: Oxide Thic
Slide 63: AA STI OXIDE CMP [CHEMICAL MECHANICAL PLANARIZATION]
AA STI OXIDE CMP [CHEMICAL MECHANICAL PLANARIZATION] • In the CMP Area a polishing process is used to remove the unwanted oxide on the surface, leaving the trenches filled with oxide. • Note: The silicon nitride film, deposited near the beginning of the flow, effectively stops the CMP process. This
Slide 64: Chemical Mechanical Planarization (CMP)
Chemical Mechanical Planarization (CMP) • CMP is used to reduce or eliminate topography on the wafer surface. A planar surface is CMP “Stop on Film” process: on-tool sensors allows this process to detect the necessary for photo to print patterns at very different hardness or optical properties of ma
Slide 65: AA STI NITRIDE WET ETCH [WET PROCESS]
AA STI NITRIDE WET ETCH [WET PROCESS] • The nitride film is no longer needed, so in the Wet Process Area wet chemicals are used to completely remove the nitride with minimal impact to the exposed oxide or silicon layers. • A second wet chemical process removes the original Pad Oxide, exposing bare s
Slide 66: TG GATE OXIDE GROWTH [DIFFUSION]
TG GATE OXIDE GROWTH [DIFFUSION] • In the Diffusion Area a thin film of high-quality silicon dioxide is grown on the surface of the silicon wafer. This oxide will be an important part of the gates of the CMOS transistors: the gate oxide. Metrology: Oxide Thickness: <3 nm Detail Close-up P-Well S
Slide 67: TG GATE POLYSILICON DEPOSITION [DIFFUSION]
TG GATE POLYSILICON DEPOSITION [DIFFUSION] • In the Diffusion Area a polycrystalline silicon film (known as “poly”) is deposited on top of the gate oxide. The poly will be the electrodes of the transistor gates. • Note: The poly is doped N-type or P-type, shown as purple (N-type) or pink (P-type) in
Slide 68: TG GATE METAL DEPOSIT [PVD]
TG GATE METAL DEPOSIT [PHYSICAL VAPOR DEPOSITION (PVD)] • In the PVD Area a metal film is deposited on top of the polysilicon film. This will form the conductive part of the transistor gates. Note: Several different types of metals may be used for this step Metrology: Metal Thickness: ~20 nm Det
Slide 69: Physical Vapor Deposition (PVD)
Physical Vapor Deposition (PVD) • Many of the metal films in the process are deposited using Physical Vapor Deposition (PVD) technology (also known as “sputtering”). • Ions bombard a metal target. The sputtered metal deposits on the wafer. • The process involves little or no chemistry and takes plac
Slide 70: TG CAP OXIDE DEPOSIT [CVD]
TG CAP OXIDE DEPOSIT [CVD] • In the CVD Area a thick film of silicon dioxide is deposited to protect the gate metal layer from corrosion and damage. This film is called Cap Oxide in this case. • Note: Some technologies use silicon nitride for this purpose. • Metrology: • Oxide Thickness: ~50 nm Deta
Slide 71: TG HARDMASK LAYERS DEPOSIT TG GATE PHOTO PATTERN
TG HARDMASK LAYERS DEPOSIT TG GATE PHOTO PATTERN Deposit hardmask layers for patterning the The “TG” mask is used to define the pattern in transistor gates. photoresist for the gates of the CMOS devices. The Metrology: pattern also electrically connects the transistor gates to each other. Ca
Slide 72: TG HARDMASK DRY ETCH, RESIST STRIP, GATE DRY ETCH
TG HARDMASK DRY ETCH TG RESIST STRIP [WET PROCESS] • A plasma process is used to transfer the TG photoresist • Plasma and wet chemistry are used to remove the pattern into the underlying hardmask layers. remaining carbon after the gate etch is complete. • 3D model shows the structures after this ste
Slide 73: TG SPACER OXIDE DEPOSIT [CVD]
TG SPACER OXIDE DEPOSIT [CVD] • A thin film of silicon dioxide is deposited to form a spacer on the sidewalls of the gate. The spacer will protect the gate metal from corrosion and is used to ensure the source/drain implants will be correctly aligned to the gate. Detail Close-up Spacer Oxide AA STI
Slide 74: TG SPACER OXIDE DRY ETCH [DRY ETCH]
TG SPACER OXIDE DRY ETCH [DRY ETCH] • A specially-designed plasma process is used to etch the spacer oxide from the horizontal surfaces while the oxide remains intact on the sidewalls of the gates. Detail Close-up Spacer Ox AA STI Ox P-Well Silicon TG = Transistor Gates 74
Slide 75: NA N-Source/Drain Photo Pattern, Implant, Resist Strip
NA N-SOURCE/DRAIN PHOTO PATTERN NA RESIST STRIP [WET PROCESS] • The “NA” mask opens up the NMOS transistors to receive • Plasma and wet chemistry are used to remove the the N source/drain implant. A thick resist is used to block the photoresist after the implant is complete implant in the areas that
Slide 76: PA P-Source/Drain Photo Pattern, Implant, Resist Strip
PA P-SOURCE/DRAIN PHOTO PATTERN PA RESIST STRIP [WET PROCESS] • The “PA” mask opens up the PMOS transistors to receive Plasma •• PA and wet RESIST chemistry STRIP [WETare used to remove the PROCESS] the P source/drain implant. A thick resist is used to block photoresist after the implant is complete
Slide 77: CN CONTACT OXIDE DEPOSIT [CVD]
CN CONTACT OXIDE DEPOSIT [CVD] Q) What do you think • A thick film of silicon dioxide is deposited to protect the CMOS transistors. is the next Traveler step? CMOS = Complimentary Metal Oxide Semiconductor Transistor 77
Slide 78: CN CONTACT OXIDE CMP [CMP]
CN CONTACT OXIDE CMP [CMP] • A polishing process is used to planarize the wafer surface to improve photo patterning of contacts. In this case a CMP “Stop in Film” timed process is used. Metrology: Oxide thickness remaining over gates: ~150 nm Detail Close-up Spacer Ox AA STI Ox P-Well Silicon 78
Slide 79: CN Hardmask Layers Deposit, Contact Photo Pattern
CN HARDMASK LAYERS DEPOSIT CN CONTACT PHOTO PATTERN • Deposit hardmask layers for patterning the contacts. • The “CN” mask is used to define the pattern in photoresist Metrology: for the contacts. The contacts will provide vertical Carbon Hardmask Thickness: ~100 nm conductive paths (wires) from
Slide 80: CN Contact Dry Etch, Resist Strip
CN CONTACT DRY ETCH CN RESIST STRIP [WET PROCESS] • A plasma process is used to etch holes in the hardmask • Plasma and wet chemistry are used to remove the layers, and down through the oxide films. The etch has remaining carbon after the contact etch is complete. selectivity to stop on the sources
Slide 81: CN CONTACT METAL DEPOSIT [CVD]
CN CONTACT METAL DEPOSIT [CVD] • A conductive metal layer is deposited to fill the contact holes. CVD tungsten (W) Q) What do you think is chosen to completely fill the holes without creating voids. is the next Traveler Metrology: Metal Thickness: ~150 nm step? Detail Close-up Spacer Ox AA STI Ox
Slide 82: CN CONTACT METAL CMP [CMP]
CN CONTACT METAL CMP [CMP] • A polishing process is used to remove all the metal on the surface (known as Q) What do you think “overburden”), leaving only the contacts filled with metal. is the next Traveler step? Detail Close-up CN Contact Metal CN Contact Metal Spacer Ox AA STI Ox CN Contact Metal
Slide 83: M1 METAL1 OXIDE DEPOSIT [CVD]
M1 METAL1 OXIDE DEPOSIT [CVD] • A thick film of silicon dioxide is deposited to serve as the foundation for the formation of the first metal interconnect layer. Note: Most chips will have multiple levels of metal interconnects. In this example, we will only show one level. Metrology: Oxide Thickness
Slide 84: M1 Hardmask Layers Deposit, Metal1 Photo Pattern
M1 HARDMASK LAYERS DEPOSIT M1 METAL1 PHOTO PATTERN • Deposit hardmask layers for patterning the metal • The “M1” mask is used to define the pattern in photoresist interconnects. for the first level of metal interconnects. The interconnects Metrology: will provide horizontal conductive paths (wires
Slide 85: M1 Metal1 Dry Etch, Resist Strip
M1 METAL1 DRY ETCH M1 RESIST STRIP [WET PROCESS] • A plasma process is used to etch trenches in the M1 oxide • Plasma and wet chemistry Q) What do you think layer. The etch must be deep enough to expose the top of are used to remove the is the next Traveler the CN metal contacts. remaining carbon af
Slide 86: M1 METAL1 METAL DEPOSIT [WET PROCESS]
M1 METAL1 METAL DEPOSIT [WET PROCESS] • A conductive metal layer is deposited to fill the trenches. Copper (Cu) is chosen for low resistivity. A special wet chemical process known as “electroplating” is used to deposit the copper. Metrology: Metal Thickness: ~250 nm Detail Close-up CN Contact Meta
Slide 87: Wet Process – Electroplating
Wet Process – Electroplating • Copper is uniquely deposited via electroplating. • The wafer is immersed in a solution of copper sulfate. An electric current is forced through the solution, and copper ions are transported from a target to the wafer. • Electroplating effectively fills deep trenches an
Slide 88: M1 METAL1 CMP [CMP]
M1 METAL1 CMP [CMP] • A polishing process is used to remove the overburden metal on the surface, leaving the trenches filled with copper. Note: The process of forming metal interconnects by filling trenches with metal and then using CMP to remove the surface metal is known as “damascene”. (Due to re
Slide 89: BP PASSIVATION DEPOSIT [CVD]
BP PASSIVATION DEPOSIT [CVD] • A thick film of silicon nitride, known as “passivation”, is deposited to protect the fragile circuits and devices from moisture, contamination, and damage. • Large holes (not shown) will be etched into the passivation to allow for electrical testing and to connect the
Slide 90: Key Terminology Glossary
Key Terminology Glossary 90
Slide 91: Glossary
Glossary Term or acronym Definition/description Anneal The anneal process exposes the wafer to high temperatures for a specific amount of time. These high temperatures enable the diffusion and activation of dopants. Anneal can also be used to relieve stress, densify films and repair implant damage,
Slide 92: Glossary
Glossary Term or acronym Definition/description Diffusion One of the ten fab areas. In the Diffusion area there are vertical furnaces where a batch of up to 125 wafers can be loaded at a time in a boat. Gases are introduced through injectors. Different process take place in the diffusion area like o
Slide 93: Glossary
Glossary Term or acronym Definition/description Mask A masks is used as part of the photolithography process. A mask is a plate that has a pattern. Parts of the plate are opaque, and parts of the plate are transparent. The transparent regions of the mask allow ultraviolet light to pass through so th
Slide 94: Glossary
Glossary Term or acronym Definition/description Planarization See CMP RDA Real-time Defect Analysis. One of the ten fab areas. RDA inspects wafers at critical points in the manufacturing process to identify and categorize defects. Defects can cause die failure. The information RDA gathers is used by
Slide 95: Document Updates
Document Updates 95
Slide 96: Document Updates
Document Updates Date Description January • Added goals, objectives and target audience 2025 • Added Construction Analogy (slide 14) • Added schematics to Wafer Processing Areas slide (slide 15) • Added photo of diffusion vertical batch (slide 28) • Added slide on Reticles (slide 35) • Added slide o
Slide 97: © 2020-2025 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject
© 2020-2025 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Statements regarding products, including statements regarding product features,