Andes Technology Corp. · TWSE:6533
Andes Technology — Q3 2023 Earnings Presentation
51 slides from Andes Technology's earnings presentation, Nov 9, 2023
Slide 1: INARA th APRA)
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Slide 2: 投資安全聲明
投資安全聲明 除簡報內所提供之歷史信息外，簡報事項係屬預測性陳述，受 到風險及不確定性因素影響，可能造成實際結果與陳述內容發 生不符，這些不確定性因素包括但不限於：天氣、競爭性產品 及其定價的影響、產業及市場對半導體產品之供給及需求移轉 、新產品大量量產之能力、技術急遽演進、半導體產業景氣以 及整體經濟環境之變化。 2
Slide 3: 簡報大綱
簡報大綱 01 公司簡介 02 營運成果 03 產品應用 04 新產品及生態系統 05 總結 3
Slide 4: 公司簡介
公司簡介 http://www.andestech.com
Slide 5: 晶心亮點
晶心亮點 • 2005年3月設立於台灣新竹科學園區。 • 根基穩健的高科技上市公司。 • 員工人數超過450人；80%為工程師。 • 獲得TSMC 2015年新的 IP OIP Award 。 • 晉升為RISC-V國際聯盟(前身為RISC-V基金會) 首席會員。 (2020) • 獲得Al Global Media頒發「2020年最傑出嵌入式處理器IP供應商」。 • EE Awards亞洲金選獎 -「Taiwan 產品獎」,「Asia 企業獎」(2021) • 2023亞太區 前五百大高成長企業 晶心任務 • 創新架構高效能/低功耗嵌入式處理器。 晶心利基 • 智能及環保之電子設備 • 雲端
Slide 6: 重要里程碑
重要里程碑 ❖ 300+ commercial licensees ◼ Geographically distributed in Taiwan, China, Korea, Japan, Europe, and USA Andes- ◼ 600+ license agreements signed Embedded SoC ❖ AndeSight™ IDE: ◼ 25,000+ installations IP / EDA Design Service / Foundries ❖ Eco-system: ◼ 500+ partners Development Environment Misc
Slide 7: 營運成果
營運成果 http://www.andestech.com
Slide 8: 2023年第三季營業收入
2023年第三季營業收入 YoY QoQ +38.2 % -8.7 % (單位:新台幣千元) 8
Slide 9: 2023年前三季營業收入
2023年前三季營業收入 YoY +4.7 % (單位:新台幣千元) 9
Slide 10: 2023年前三季 前十大客戶之應用分析
2023年前三季 前十大客戶之應用分析 單位: 新台幣千元 10
Slide 11: 2023年第三季度 權利金收入
2023年第三季度 權利金收入 QoQ YoY +38.7 % +3.9 % (單位:新台幣千元) 11
Slide 12: 2023年前三季權利金收入
2023年前三季權利金收入 YoY -10.9 % (單位:新台幣千元) 12
Slide 13: 2023年前三季權利金應用分析
2023年前三季權利金應用分析 單位: 新台幣千元 13
Slide 14: 2023年前三季營收分析 (by type)
2023 A= ES WEA H-WLA st m License Fee @ Running Royalty ® Maintenance @ Others yRISCc-v’ 14
Slide 15: 2023年前三季營收分析 (by region)
2023 A= ZS WE H-tH | Taiwan @ USA China @Korea MJapan ® Europe MRISC- 15)
Slide 16: 2023年前三季權利金分析 (by product)
2023F HF HSA i-H mal m N25 4 mRISC-V N8 mV3 N9 ACE N45 NX27 N10 A4S N13 NX25 LLVM D25 N7 D10 E8 tm AE250 A27 Pipeline OTHERS PRISC-v’ 16 ANibes TECHNOLOGY
Slide 17: 2023年前三季 銷售分析- RISC-V
2023年前三季 銷售分析- RISC-V (單位:新台幣千元) 17
Slide 18: 歷年收入分析
(NT$) 歷年收入分析 License Royalty 18
Slide 19: 2023年第三季度 營業毛利與毛利率
2023年第三季度 營業毛利與毛利率 (單位:新台幣千元) 19
Slide 20: 2023年前三季營業毛利與毛利率
2023年前三季營業毛利與毛利率 (單位:新台幣千元) 20
Slide 21: 2023年第三季度 營業費用
2023年第三季度 營業費用 QoQ YoY -1.5 % +32.3 % (單位:新台幣千元) 21
Slide 22: 2023年前三季營業費用
2023年前三季營業費用 YoY +37.8 % (單位:新台幣千元) 22
Slide 23: 2023年第三季度 營業利益(損失)
2023年第三季度 營業利益(損失) QoQ YoY -% -% (單位:新台幣千元) 23
Slide 24: 2023年前三季營業利益(損失)
2023年前三季營業利益(損失) YoY -% (單位:新台幣千元) 24
Slide 25: 2023年第三季度 合併淨利(損)
2023年第三季度 合併淨利(損) QoQ YoY -% -64.4 % (單位:新台幣千元) 25
Slide 26: 2023年前三季合併淨利
2023年前三季合併淨利 YoY -98.5 % (單位:新台幣千元) 26
Slide 27: 2023年第三季度 每股盈餘
2023年第三季度 每股盈餘 QoQ YoY +2.88 $ -3.72 $ (單位:新台幣元) 27
Slide 28: 2023年前三季 每股盈餘
2023年前三季 每股盈餘 YoY -9.50 $ (單位:新台幣元) 28
Slide 29: 產品應用
產品應用 http://www.andestech.com
Slide 30: 晶心RISC-V核心在SoC中被採用的數目
晶心RISC-V核心在SoC中被採用的數目 o single core ooooo oooooooooooooooooooo…oooooooooooooooooooo 2-8 cores ooo oooooooooooooooooooo…oooooooooooooooooooo oooooooooooooooooooo…oooooooooooooooooooo oooooooooooooooooooo…oooooooooooooooooooo oooooooo oooooooooooooooooooo…oooooooooooooooooooo oooooooo oooooooooooooooo
Slide 31: Andes RISC-V Powering Rich Applications
Andes RISC-V Powering Rich Applications Mobile Cloud AI Space N25F, N45 D25F, D45, AX25MP, AX45MP Endpoints. Edge. Cloud. Space. Secure, control, compute, communicate, position Accelerate, accelerate, accelerate NX27V, AX25, AX27, AX45MP, N25F AX45MPV N25F, N45, AX45MP N25F, A25, A45MP, AX45MP Subje
Slide 32: MTIA: Meta Training and Inference Accelerator
MTIA: Meta Training and Inference Accelerator ◼ ISCA 2023 paper, “MTIA: First Generation Silicon Targeting Meta’s Recommendation Systems” ◼ Proc-A/B: Andes AX25-V100, an early version of the popular NX27V ◼ Custom extensions: for new interfaces, instructions and registers ◼ Performs quite well on lo
Slide 33: New Products and Ecosystems
New Products and Ecosystems http://www.andestech.com
Slide 34: 晶心RISC-V產品路線圖
晶心RISC-V產品路線圖 RV32/RV64 Vector Ext. Superscalar Out of Order A25MP 27-Series: 45-Series: 60-Series: Cache-Coherent 1-4 Cores AX25MP Vector Ext. Dual Issue > 2.5 GHz MemBoost Vector Ext. > 2x per-GHz MemBoost performance of NX27V Linux with A25 A27/AX27 N45/NX45/D45 45-Series FPU/DSP AX25 A27L2/AX27L
Slide 35: AndesCore AX65 OOO Application Processor
AndesCore™ AX65 OOO Application Processor ⚫ 13-stage 4-way 64-bit OOO processor B1 F1 F2 D1 D2 D3 I1 I2 E1 E2 E3 E4 ⚫ RVA22+ profile ALU WB x3 issue, +br & misc WB x1 ⚫ Multicore cluster up to 8 cores batch, fetch, decode, rename, register align & buffer dispatch memory WB x2 read ⚫ 8 Execution Pipe
Slide 36: Roadmap for the AX60 Series
Roadmap for the AX60 Series AX67 RVA24 and most performant AX66 AX65 Multi-cluster AX63 Balanced Power-optimized Efficient Mid-range Extended AX60 Series: 13-stage OOO Linux MP Subject to change without notice copyright © 2021-2023 Andes Technology Taking Mainstream 36
Slide 37: AX45MPV Multicore Cluster
AX45MPV Multicore Cluster ◼ At multicore cluster level: ⚫ Up to 8 cores ⚫ CM/L2$ subsystem – 128KB to 8MB, 64B line, 16-way – Multi-cycle support for high-density SRAMs – I/D prefetch, up to 64 outstanding requests ⚫ AXI Bus Interfaces up to 512 bits SPP ◼ Scalar Unit: RV64GCBP ⚫ 8-stage In-order du
Slide 38: AX45MPV: 1024-bit Vector Processor
AX45MPV: 1024-bit Vector Processor ◼ RISC-V Vector Extension (RVV v1.0) F1 F2 ID II EX MM LX WB ⚫ data format: int8~64, fp16~64; int4, bf16 ⚫ VLEN/DLEN: 128~1024 bits, 1:1 or 2:1 ratio ⚫ Up to 6 DLEN results per cycle ◼ Efficient support needed for tight coupling with HWE 1. Data exchange performanc
Slide 39: Andes is Driving Innovations in Automotive
Andes is Driving Innovations in Automotive with Industry’s 1st RISC-V ISO 26262 Fully Compliant Core, N25F-SE In-Cabin Radar CMOS Sensor Radar Host Subsystem Controller N25F-SE N25F-SE Radio Memory Peripheral Auto TDDI Auto MCU Auto Storage Subject to change without notice Copyright© 2021-2023 Andes
Slide 40: AndesCore RISC-V Functional Safety Roadmap
AndesCore™ RISC-V Functional Safety Roadmap High Performance Mission Critical 60-Series 13-stage, OoO D45-SE Computing Power 4-issue Mainstream 8-stage Processing Dual-issue ASIL-D Compliant (planning) ASIL-D Compliant D25F-SE ASIL-B Supported Low Power N25F-SE 5-stage IP: Q4, 2023 & Security 5-stag
Slide 41: N25F-SE, D25F-SE 5-Stage, ASIL-B Full Compliant
N25F-SE, D25F-SE 5-Stage, ASIL-B Full Compliant ◼ CPU Core ⚫ 5-stage, in-order, single-issue architecture ⚫ RISC-V RV32 GCB[P]* ISA, with Andes Extensions – D25F-SE with the RVP (SIMD/DSP) instruction extension – RVB bit-manipulation instructions for cryptography, … applications ⚫ AndeStar™ V5 32-bi
Slide 42: AndesCore N25F-SE Certified by ISO 26262
AndesCore™ N25F-SE Certified by ISO 26262 ◼ “The product has been approved in compliance with ASIL B requirements” ◼ ISO 26262 Edition 2018, parts: ⚫ ISO 26262-2:2018 ⚫ ISO 26262-4:2018* ⚫ ISO 26262-5:2018 ⚫ ISO 26262-8:2018 ⚫ ISO 26262-9:2018 ◼ Certification Body ⚫ SGS-TÜ V Saar GmbH ⚫ SGS-TÜ V Saa
Slide 43: D45-SE 8-Stage, Dual-Issue, up to ASIL-D
D45-SE 8-Stage, Dual-Issue, up to ASIL-D ◼ CPU Core ⚫ 8-stage, in-order, superscalar, dual-issue most instruction pairs ⚫ RISC-V RV32 GCBP* support, Andes Extensions ⚫ AndeStar™ V5 32-bit architecture ◼ Memory Subsystem ⚫ Instruction and data cache, up to 64KB ⚫ Instruction and data local memory, up
Slide 44: D23: Compact Controller for IoT/MCU/ECU
D23: Compact Controller for IoT/MCU/ECU ◼ 3-stage, limited dual-issue (optional) >1000 PMU Debug Trace Interrupts ◼ ISA extensions: ⚫ Base: RV32 I/E-MAC + B + Zce CLIC WFI / WFE Debug & Trace I/F ⚫ Advanced: FD + P + K + CMO 3-stage uCore, ePMP/sPMP/PMA Timer ◼ Privilege modes: M, S, U DSP FPU ACE ◼
Slide 45: D23: Compact Controller for IoT/MCU/ECU
D23: Compact Controller for IoT/MCU/ECU ◼ Memory subsystem: ⚫ Caches: ➢ Config: RISC-V Code Size Benchmarks • Icache only: ifetch IMAC + V5 IMABC + V5 IMABZce + • RO-cache (Read-Only): ifetch and load ISA IMAC (N22) (N25F) V5 (D23) • I/D caches: ifetch, load and store SPEC CPU 2,840 2,360 -16.9% 2,3
Slide 46: Security System Architecture for D23 (D23-SE)
Security System Architecture for D23 (D23-SE) • Create multiple zones protection by PMP/sPMP • REEs (Rich Execution Environment) • TEEs (Trusted Execution Environment) • IOPMP for IO protection REE TEE … FuSaEE Supervisor Mode Secure Monitor Machine Secure Boot Mode Andes RISC-V Cores ie D23 (D23-SE
Slide 47: Taking RISC-V Mainstream
Subject to change without notice Copyright© 2021-2023 Andes Technology Taking RISC-V® Mainstream 47
Slide 48: AndesAIRE AnDLA I350
AndesAIRE™ AnDLA™ I350 • Andes Deep Learning Accelerator (AnDLA™) AnDLA™ I350 • High performance-efficient deep learning accelerator for edge and end-point inference • General Matrix Scalable and multi-DLA DMA Multiply • Cooperate with AndesCore™ full series (22/23/25/27/45/65) • Accelerating for mo
Slide 49: Taking RISC-V Mainstream
Subject to change without notice Copyright© 2021-2023 Andes Technology Taking RISC-V® Mainstream 49
Slide 50: Taking RISC-V Mainstream
Subject to change without notice Copyright© 2021-2023 Andes Technology Taking RISC-V® Mainstream 50
Slide 51: Thank You
Thank You http://www.andestech.com +886-3-5726533 51