Andes Technology Corp. · TWSE:6533

Andes Technology — Conference Presentation (April 2019)

23 slides from Andes Technology's conference presentation, April 2019

  1. Slide 1: Introduction to Andes Superscalar Processors: N15(F)/D15(F)

    Introduction to Andes Superscalar Processors: N15(F)/D15(F) Driving Innovations™ Vincent Chen Director 2018/7/31

  2. Slide 2: N15(F)/D15(F) - Superscalar Processors

    N15(F)/D15(F) - Superscalar Processors  AndeStar™ V3 architecture  Four AndesCore™ products  N15 : Baseline ISA  D15 : N15 + DSP extension ISA  D15F : D15+ Floating point unit  N15F : N15 + Floating point unit  6-stage dual-issue pipeline  One instruction from ALU/Multiply/Divide/DSP/Branch/

  3. Slide 3: Applications

    Applications • Touch Screen • 3D printer • PLC • ADAS • IoT gateway • Industrial automation • NB-IoT • Smart home • Sensor hub RTOS/ Linux appliances • Home automation Bare metal • HMI control system • Wireless vacuum cleaner • Surveillance  32-bit dual-issue pipeline  2700 CoreMark @T40LP  4000

  4. Slide 4: AndesCore: Product Lineup (V3 Arch.)

    AndesCore™ : Product Lineup (V3 Arch.) Ultra Low Power Mainstream High Performance D15 E830 D15F D1088 N15 S801 N1337 N15F N1068 N968 Floating Point N820 N705 MMU(Linux) Static Branch Pred. I/D Cache BTB BTB FlashFetch AHB/AHB2/AXI Bus AHB-lite/APB Bus ECC 32-bit GPR, Multiplier, HW divider, Vector

  5. Slide 5: AndesCore: Product Lineup (V3 Arch.)

    AndesCore™ : Product Lineup (V3 Arch.) Bare Metal, RTOS-based Applications Linux-based Applications D15 E830 D15F D1088 N15 S801 N1337 N15F N1068 N968 Floating Point N820 N705 MMU(Linux) Static Branch Pred. I/D Cache BTB BTB FlashFetch AHB/AHB2/AXI Bus AHB-lite/APB Bus ECC 32-bit GPR, Multiplier, HW

  6. Slide 6: Functional Blocks

    Functional Blocks  Pwr. mgmt. instruction  5-wire JTAG debug I/F  Powerbrake &  Trace I/F to Trace module QuickNap™ technology (EDM: Embedded Debug Module)  32 vector interrupts Standby  Memory Mgmt. EDM & & VIC Trace I/F Unit (Linux ready)  Single-cycle multiplier  Memory protect  Radix-4

  7. Slide 7: StackSafe to Protect Stack Usage

    StackSafe™ to Protect Stack Usage  Recording mode:  Record the maximum usage of stack pointer maximum 15 Stack Usage 10 5 0 time  Protection mode:  Allocate stack size and set its bound accordingly  When stack pointer grows over the bound Exception ! 20  Generate an exception 15 Stack Usage 10

  8. Slide 8: Power Management

    Power Management PowerBrake to digitally adjust power (via stalling pipeline) QuickNap™: logic power-down and SRAM in retention Power maximum consumption performance minimum performance Standby QuickNap™ (logic power-down and SRAM in retention) Dormant SRAM power-down Shutdown Performance (frequen

  9. Slide 9: AndeStar DSP ISA Extension (1/2)

    AndeStar™ DSP ISA Extension (1/2) Features:  > 130 instructions  Saturation and Rounding  Data types: fractional (Q31, Q15, and Q7) and integer (32b, 16b, 8b)  16-bit and 8-bit SIMD instructions 16-bit: +, -, x, min, max, abs, clip, compare, <<, >>, signed, unsigned 8-bit: +, -, min, max, abs

  10. Slide 10: AndeStar DSP ISA Extension (2/2)

    AndeStar™ DSP ISA Extension (2/2) SW support:  Intrinsic functions for using instructions in C.  Compiler generation of SIMD instructions based on vector data type. >200 DSP-ISA-optimized DSP libraries  110% performance boost with DSP ISA (average of integer functions) 10 Driving InnovationsTM

  11. Slide 11: Andes DSP Library

    Andes DSP Library Basic math: vector mathematics Fast math: sin, cos, atan, atan2, sqrt, etc. Complex math Statistics: max, min, RMS, etc. Filtering: IIR, FIR, LMS, etc Transforms: FFT, DCT/DCT4 Matrix functions PID controller, Clark and Park transforms MISC: copy/fill arrays, data type con

  12. Slide 12: Floating Point Unit (FPU)

    Floating Point Unit (FPU)  IEEE 754 Compliant  Single (32-bit) or Double (64-bit) precision configuration  Register number configuration  Single precision: 32  Double precision: 16 or 32  Support all rounding modes and exceptions  Support Flush-To-Zero mode to speedup denormalized number proc

  13. Slide 13: AMR-WB Performance

    AMR-WB Performance N10 D10 D15 MAX 337.07 85.58 58.24 AMR-WB AVG 289.16 73.13 49.99 Encode MIN 188.50 51.47 33.20 MAX 75.27 25.21 15.25 AMR-WB AVG 66.61 21.96 13.54 Decode MIN 54.77 18.22 11.07 The benchmarking numbers are in MCPS. (Million Cycle Per Second) For all the test vectors, the maximum (MA

  14. Slide 14: Support and Service

    Support and Service 14 Driving InnovationsTM

  15. Slide 15: Overview of Andes Technology Corporation

    Overview of Andes Technology Corporation Andes Highlights • Founded in March 2005 in Hsinchu Science Park, Taiwan, ROC. • Core RD team from AMD, DEC, Intel, MIPS, nVidia, and Sun. • Just over 140 people; 80% are engineers. • EETimes' Silicon 60 Hot Startups to Watch (2012) • TSMC OIP Award “Partner

  16. Slide 16: AndeSight: Professional IDE (1/2)

    AndeSight™: Professional IDE (1/2)  Eclipse-based  Project Setup:  Meta Linker Script Editor  Flash ISP configured through GUI  Debug Support:  Script-Based RTOS Awareness  Virtual Hosting  Register Bitfield Viewing/Update Task  Break-n-Display on Exceptions List Resource Usage 16 Driving I

  17. Slide 17: AndeSight: Professional IDE (2/2)

    AndeSight™: Professional IDE (2/2)  Program Analysis  Function Profiling  Performance Meter  Code Coverage  Function Code Size  (Static) Stack Size  Debug/Analysis for Arduino  Custom Plugin Intf 17 Driving InnovationsTM

  18. Slide 18: AndeShape, AndeSoft IP Support

    AndeShape™, AndeSoft™ IP Support  AndeShape™ Platform IPs  AE300: AXI fabric package for scalable SoC applications  AE210P: generic platform IP for micro-controllers  AXI Bus Components:  AXI bus matrix, bus bridges  AXI up/downsizer  AHB Bus Components:  AHB bus matrix, bus bridge, decoder

  19. Slide 19: Andes IoT Stack

    Andes IoT Stack ► Andes6 connectivity components ► Contiki RTOS for OS services ► An implementation of 6LoWPAN (IPv6 over 802.15.4) ► Commercial (e.g. InsideSecure) or open source TLS for security ► Connecting to the Clouds (Microsoft Azure, Acer BYOC) MQTT | CoAP TLS | DTLS TCP | UDP IPv6 Andes6 (6

  20. Slide 20: Andes Ecosystem

    Andes Ecosystem IP Design Service / Foundries SW and Development Environ. EDA/Others 20 Driving InnovationsTM

  21. Slide 21: Andes Technical Support

    Andes Technical Support Pre-Sales Post Sales • AndesCore™ Introduction • AndesCore™ Synthesis Report • Customizable Training Courses • Code Size Optimization • SoC Design Consulting • SoC Evaluation Consulting • E-service Support • A web-based supporting system • A systematic way to get Andes techni

  22. Slide 22: Concluding Remarks (1/2)

    Concluding Remarks (1/2) WHY Andes  Patented processor architecture  Leading performance efficiency Strong on cost performance Strong on power efficiency  Intuitive standard SW development tools  Comprehensive SW stacks  Flexible platform solutions  Elite third parties  Responsive/experien

  23. Slide 23: Concluding Remarks (2/2)

    Concluding Remarks (2/2)  WHY N15(F)/D15(F)  Performance  Extreme HIGH Computing Power  5.41 CoreMark/MHz; 3.36 DMIPS/MHz;  2700 CoreMark in TSMC 40LP process node; 4000 CoreMark in TSMC 28HPM process mode  Low Latency and Fast Response Time  Power Consumption  Compact Core  Optimized Memor

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