Infineon Technologies Ag · XETR:IFX
Infineon Technologies — Technical Presentation (November 2002)
44 slides from Infineon Technologies's technical presentation, November 2002
Slide 1: Technical Presentation TriCore 32-bit Unified Processor
Technical Presentation November 2002 TriCore™ 32-bit Unified Processor Never Stop T h i n k i n g. 1
Slide 2: TriCore Value Proposition
TriCore Value Proposition TriCore™ is a 32-bit superscalar unified MCU-DSP processor architecture, with fast interrupt response, optimized for cost sensitive,real-time embedded systems. It is available as a licensable core in both VHDL and Verilog. 2
Slide 3: Best-in Class Performance
Best-in Class Performance TriCore™ is ONE core that offers: • Best-in-class microprocessor performance – 1.5 MIPS/MHz • Best in class controller performance - 2 cycles context switching • Best-in-class DSP performance - 2 taps/cycle for FIR filters www.infineon.com/tricore 3
Slide 4: Unified Processor Reduces Complexity & Cost
Unified Processor Reduces Complexity & Cost 1 processor does the work of 2. RTOS + DSP + App No need for inter-processor communication Dynamic assignment of DSP vs. TriCore™ controller code in response to changes in the system requirements Memory I/O Fast context switch is the key Reduced nu
Slide 5: Target Segments
Target Segments Automotive Industrial Control Data Storage & • Engine Management • Robotics Processing • Transmission Control • PLC’s • Hard Disk Drives • ABS • Servo-Drives • Tape Drives • Motor Control • Scanners • Active Suspension • Power-Inverters • Infotainment • Digital Copiers • Machine-Tool
Slide 6: TriCore Unique 3-in-1 Feature Set
TriCore™ Unique 3-in-1 Feature Set! Microcontroller • Fast interrupt response • Fast context switch • Low code size through use of 16-bit & 32-bit instructions • Powerful bit manipulation unit • Powerful comparison instructions • Integrated peripheral support DSP RISC Processor • Sustainable single-
Slide 7: TriCore Core Roadmap
TriCore™ Core Roadmap Performance TC 3 1500MIPS lit y i b i at TC 2 mp 600MIPS Co TC 2 Performance / Power TC1Modular Enhancements Softmacro TC 1 v1.3 Available 250MIPS TC 1 v1.3 TC1ML Low Power Small Footprint 100MIPS TC 1 v1.2 2000 2001 2002 2003 7
Slide 8: The Infineon Open Licensing Program (OLP)
The Infineon Open Licensing Program (OLP) Infineon has created a licensing program which allows semiconductor companies, OEMs and design houses to gain access to Infineon IP. This program will ensure that Infineon Cores become industry standards with: • A broad tool partner base • A wide range of ap
Slide 9: SOC Design Trend: Step-up on a Platform!
SOC Design Trend: Step-up on a Platform! Q. Why a platform? Complete, silicon tested A. Because Designers need a fast, easy system based on one or and reliable way to complete their system more open standard buses Configurability to allow MP System optimisation for both performance & cost Extensive
Slide 10: Basic TC1MP-S Configuration
Basic TC1MP-S Configuration TC1M = CPU + PMI + DMI P-TAG MMU D-TAG Verified in >10 Silicon Implementations TC1M PMI: Program Memory Interface P_MEM PMI CPU DMI D_MEM DMI: Data Memory Interface LMBh: Local Memory Bus hub FPU LMBh Fast local bus operating at CPU speed CPS FPI: Flexible Peripheral Inte
Slide 11: Structure of a TriCore-based SOC
Structure of a TriCore-based SOC Key LMU required EBU PLL optional STM D-RAM SOC UDL P-RAM AMBA Bridge ASL User-defined Coprocessor LFI BCU LMBh ICU Debug P-Tag MMU D-Tag FPU TC1MP-S configurable TC1M CPU + PMI + DMI 11
Slide 12: TC1MP-S: General View & Connections
TC1MP-S: General View & Connections Data Tag Program Tag MMU Interface Interface Interface TC1MP-S Program Memory Data Memory P-TAG MMU D-TAG Interface Interface TC1M PMI CPU DMI Memory Local Memory BIST Bus Interface Interface FPU LMBh CPS Interrupt LFI FPI Bus FPI Bus Interface Interface Debug Clo
Slide 13: TC1MP-S: Silicon Proven Softmacro
TC1MP-S: Silicon Proven Softmacro SOFTMACRO MEMORY TC1MP-S 24K P-SPRAM P-TAG MMU D-TAG + 24K D-SPRAM 8K P-cache TC1M PMI CPU DMI 8k D-cache FPU LMBh CPS LFI FPI Bus HARDMACRO 10.3 mm2 - 0.18µm 150 MHz w/c TC11IB PXF 4225 SILICON 13
Slide 14: Accelerating Implementation
Accelerating Implementation TriCore TC1MP-S based Hardmacro TC1M = CPU + PMI + DMI I-TAG MMU D-TAG 32kBytes total memory 16k Data, with 8k Cache 16k Program, with 8k Cache MMU D Mem P Mem LMBH, LFI, ICU, Debug TC1M Area ~ 8.44 mm2 (0.18µm) Frequency: 200 MHz (1.62V, 125C, typical 0.18µm
Slide 15: TriCore TC1MP-S: Points of Interest
TriCore TC1MP-S: Points of Interest TC1M FPI The heart of the system The gateway to a wealth of pre-verified IP’s LMBh, LFI The glue that binds the system Debug System Easy & Powerful Memory Have it your way! Software Development Tools Many to choose from Exceptions Simply the best system Benchmarks
Slide 16: TC1M: Block Diagram
TC1M: Block Diagram Program Memory 32-bit Load/Store Harvard Architecture Superscalar Execution - Issue Up To 3 TriCore TC1M Instructions Simultaneously Program Memory Interface Add Customized Instructions Using Coprocessors Data Address Coprocessor Registers Pipeline Control Registers 32, 32-bit Ge
Slide 17: TC1M: The Pipelines
TC1M: The Pipelines TriCore is the only 32-bit Superscalar Licensable Core Superscalar Processing means the ability to issue more than 1 instruction per clock cycle – TriCore can issue up to 3 instructions in parallel with automatic data resource hazard checking and handling. MAC MAC Execute 1 Execu
Slide 18: TC1M: Code Size
TC1M: Code Size 32-bit & 16-bit Instruction Formats 30% - 40% Code Size Reduction Over 32-bit Format Only Two Formats Can Be Freely Intermixed - No Mode To Change 16-bit Instructions Are Subset Of 32-bit Instructions & Are Automatically Generated During Compilation Many 3-Operand Instructions Availa
Slide 19: TC1M: Power Management
TC1M: Power Management The Power Management is under software control. TC1M implements 3 power management modes: – RUN Mode The system is fully operational, all clocks are enabled – IDLE Mode The CPU & memories clock is disabled – DEEP SLEEP Mode All the clocks are turned-off 19
Slide 20: LMBh, LFI & CPS
LMBh, LFI & CPS LMBh – Synchronous, pipelined bus with variable block transfer support – 32-bit address, 64-bit data – Central, simple per cycle arbitration – Address pipelining LFI – Bi-directional bridge between the LMB and the FPI bus – Address decoding and translation – Flexible LMB/FPI clock ra
Slide 21: TriCore TC1MP-S Memory
TriCore TC1MP-S Memory TriCore’s 4GB of address space is divided into 16 regions or segments P-TAG MMU D-TAG (0 through to 15), each of 256MB TC1M Internal Internal P_MEM PMI CPU DMI D_MEM TriCore implements a hierarchical, linear memory model using the Little Endian convention Internal LMBh D_MEM T
Slide 22: TriCore TC1MP-S Exceptions
TriCore TC1MP-S Exceptions There are 3 categories of exceptions: – Interrupts (handled by the ICU) Selectable number 3 / 15 / 63 / 255, each with its own priority Arbitration independent from CPU operation Vector interrupt support – Traps Allows the CPU to service conditions that are critica
Slide 23: TriCore TC1MP-S FPU
TriCore TC1MP-S FPU IEEE 754 compatible Supports only single precision – Small area: 0.3 mm 2 in 0.13µm process It is closely coupled to the Coprocessor interface Implements a pipelined design for fast execution The design scales to the same clock frequency as TC1M 23
Slide 24: TriCore TC1MP-S MMU
TriCore TC1MP-S MMU 4 GByte virtual address space Addressing by direct translation or via Page Table Entries (PTE) Two addressing modes: – Physical – Virtual Physical page attributes override Virtual page attributes Implements 2 Translation Lookaside Buffers (TLB) – Supports 4 page sizes: 1K
Slide 25: FPI Bus Features
FPI Bus Features Internal bus that connects TriCore core & internal peripherals Multimaster capability (up to 16 masters) Demultiplexed operation Clock synchronous Peak transfer rate of up to 400 MBytes/s (@ 100 MHz bus clock & 32-bit data bus) 32-bit wide address & data buses 8, 16 &
Slide 26: Debug System
Debug System OCDS Level 1 OCDS Level 2 = OCDS Level 1 + Expansion Trace Memories Program Flow Serial Link Emulation Probe Customer application CPU OCDS Customer application Embedded emulation: OCDS + Trace expansion: OCDS (On-Chip Debug Support) • Enhanced concept • Low cost concept Features: • Avai
Slide 27: Debug System: OCDS Overview
Debug System: OCDS Overview TC1MP-S SOC break_in break_out Debug CPU Debugger JTAG Interface JTAG Module Debug Interface OIther TC1M Resources Breakpoints; Single Stepping Read/Write Access to the whole Address Space Connection to the Debugger including JTAG and Break-Interface Fast Tracing through
Slide 28: Infineon TriCore 32-bit Architecture
Infineon TriCore 32-bit Architecture Software Generation, Debug & Calibration Tools Operating Systems Applications / Boards / Software Modeling Tools / Training / Consulting 28
Slide 29: Language Tools
Language Tools • Optimized C/C++ Cross Compiler • Full TriCore 2 Architecture support • Enhanced DSP code generation www.tasking.com • Misra C code checking support • Peripheral Control Processor support • ANSI/IEEE-754 Floating Point Libraries • Macro Assembler / Linker / Locator • EDE, Debugger, S
Slide 30: Language Tools - Continued
Language Tools - Continued • Optimized C/C++ Cross Compiler • Japanese Automotive C extensions • PCP support www.ghs.com • Macro Assembler/Linker/Locator • Run-Time Error Checking • Multi IDE, Debugger, Simulator • Version Control System • Intuitive, fully Graphical User Interface • Windows & Solari
Slide 31: Language Tools - continued
Language Tools - continued • GNU based C/C++ Cross Compiler • Macro Assembler / Linker / Locator • Debugger, Simulator • PXROS support www.hitec-rt.com • Windows, Solaris & Linux support • GNU source level debugger with GUI • Virtual I/O file based support • TGDB graphical user interface for • Solar
Slide 32: Hardware Tools
Hardware Tools www.lauterbach.com www.hitex.com www.ashling.com TRACE32-ICD TANTO VITRA TriCore Support TriCore Support TriCore Support • High-speed link via • USB (V1.1),Serial (115k • RS232 Serial Port Ethernet, ISA bus or Baud),Ethernet (10BaseT) (115Kbits/s), Ethernet LPT (RJ45/10BaseT) & • High
Slide 33: Hardware Tools - continued
Hardware Tools - continued www.signum.com www.pls-mc.com www.tektronix.com JDSnet / ET-TriCore Universal Debug Engine • Multi-threaded Windows application – • High-speed CAN in a ROM or BSL-RAM www.agilent.com Chameleon Debugger monitor version with • JDSnet/ET is a real- up to 1Mbps time, Transpare
Slide 34: Expert Systems: DAvE (Digital Application Engineer)
Expert Systems: DAvE DAvE (Digital Application Engineer) • Helps program Infineon microcontrollers that you want to use in your project. DAvE offers: • Intelligent wizards • Chip configuration • Automatic C-level templates generation (on-chip peripherals) • Interrupt controls • Helps you compare and
Slide 35: Tooling Certification & Partner Programs
Tooling Certification & Partner Programs Certification & Test TriCore Development Tools are supported by the Infineon Certification & Test Programme to ensure integrated tooling solution operation with vendor tool-chains. Partner Programs Infineon Development Tools information, updates, new releases
Slide 36: TriCore DSP Library
TriCore DSP Library TriLib • Assist Application developers with standard algorithms • Provide benchmarks for DSP applications • Significantly reduce DSP application development time • Compiler support • Implementation of common DSP algorithms which are delivered in source code • Hand-coded and optim
Slide 37: Real-Time Operating Systems
Real-Time Operating Systems 37
Slide 38: Linux – Project Goals
Linux – Project Goals •Port Embedded Linux with real-time extensions to TriCore •Provide a means for distributing, maintaining, and supporting the port once completed. •Provide sample applications to validate the port. •Provide a board support package for a TriCore evaluation board. •Provide capabil
Slide 39: Linux Port Project Deliverables
Linux Port Project Deliverables • Boot loader • Low level device drivers • Embedded Linux kernel with TCP/IP • Standard Linux library • Real-Time extensions • Memory protection and MMU support • Performance data • File system support • Utility box • Shell and standard UNIX utilities • Documentation
Slide 40: System Comparison: TC1MP-S Vs. ARM1020E
System Comparison: TC1MP-S Vs. ARM1020E ARM1020E TCMP-S Core ARM10E TC1M I-Cache 32K 8K D-Cache 32K 8K I-SPR 0K 24K D-SPR 0K 24K 64b internal I-mem I/F Yes Yes 64b internal D-mem I/F Yes 128b I/F MMU Yes Yes Dual 64b bus I/F Yes Yes Support for trace Yes Yes Interrupts 2 255 Local-to-peripheral brid
Slide 41: System Area Comparison
System Area Comparison (mm2 in 0.13µm process) 41
Slide 42: DSP Interface
DSP Interface Using data from the EEMBC telecom benchmark (out-of-box) http://www.eembc.org/ Note: TC1M data based on existing silicon (TC11IB) 42
Slide 43: TriCore TC1MP-S: Summary of Benefits
TriCore TC1MP-S: Summary of Benefits • 64-bit performance with 32-bit area / power / cost • Compact Code Size (16b/32b mix) • Powerful built-in DSP capabilities • Outstanding Real-Time Performance • Not only CPU Core, but also System IP & Peripheral Library • Tested on a variety of Process Technolog
Slide 44: TriCore Unified Processor
IriCore UNIFIED PROCESSOR Infineon techno ogres Never Stop Thinking.
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