Microsemi — Space Forum 2017
24 slides from Microsemi's conference presentation, 2017
Slide 1: RTG4 Radiation Update, Space Forum 2017
Power Matters.TM RTG4 Radiation Update Space Forum 2017 J.J. Wang, Chief Engineer Nadia Rezzak, Staff Engineer Stephen Varela, Engineer © 2017 Microsemi Corporation. Company Proprietary 1
Slide 2: Agenda
Agenda Introduction Chip Level TID and SEE Update Single Event Effects Update • Fabric Circuit Heavy-Ion Testing • PLL and SERDES Heavy-Ion Testing • Reprogramming in Space Flight Summary and Further Radiation Testing © 2017 Microsemi Corporation. Company Proprietary Power Matters.TM 2
Slide 3: RTG4 FPGAs
RTG4 FPGAs Radiation tolerant Flash-based FPGA manufactured by UMC 65nm technology High-Speed Signal Processing • 300 MHz • 150K LE (STMRFF) • 5 Mbit SRAM (EDAC) • 462 Multipliers (DSP) • RT-PLL • 24 x 3.125 Gbps SERDES Hardened for both TID and SEE • TID > 100 Krad • SEL immune • SEU/SET/SEFI
Slide 4: Flash-Cell Radiation Hardening
Flash-Cell Radiation Hardening © 2017 Microsemi Corporation. Company Proprietary Power Matters.TM 4
Slide 5: TID and SEE Hardened C-Flash Cell
TID and SEE Hardened C-Flash Cell 10 DATA Propagation Delay Change (%) Commercial 9 N-Flash FPGA 8 Switch 7 VDD(2.5) 6 5 RTG4 P-Flash 4 Radiation Tolerant 3 C-Flash FPGA VDD 2 1 PMOS 0 -1 VSS 0 25 50 75 100 125 Total Dose (krad) NOR Flash architecture VDD Charge storage for N-Flash or P-Flash is
Slide 6: Fabric Circuits Radiation Update
Fabric Circuits Radiation Update © 2017 Microsemi Corporation. Company Proprietary Power Matters.TM 6
Slide 7: Fabric FF (STMRFF) SET Filter Enable―2X Error Reduction
Fabric FF (STMRFF) SET Filter Enable―2X Error Reduction SET Filter Off 600ps Filter On No error observed at 1 MHz Flip-flop TMR works to eliminate SEU at 1 MHz Errors observed at 50 MHz, 100 MHz, and 200 MHz were all SET and not SEU Filter reduced SET by half Device Family Error Rate for GEO
Slide 8: LBNL―RTG4 Mathblock SET Filter Testing
LBNL―RTG4 Mathblock SET Filter Testing Mathblock design with SET Filter enabled vs disabled are tested • Parallel Math Block Chains (25 stages) – Configured using cascade mode uses dedicated math block routing—Not going through the fabric – Frequencies : 50 MHz and 100 MHz – SET filter enabled (60
Slide 9: Math Blocks SET Filter Enable―10X Error Reduction
Math Blocks SET Filter Enable―10X Error Reduction 100 MHz Cross Section (cm2) 1.00E-07 100MHz SET Disabled 1.00E-08 100Mhz SET Enabled 1.00E-09 0 5 10 15 20 25 30 35 40 LET (MeV-cm2/mg) 50 MHz Cross Section (cm2) 1.00E-07 50MHz SET 1.00E-08 Disabled 50 MHz SET Enabled 1.00E-09 0 5 10 15 20 25 30 35
Slide 10: Global Clock Buffer
Global Clock Buffer No SET observed in Global Buffer or Row Global Buffer for LET < 30 MeV-cm2/mg Notes: Data points indicate testing limits. © 2017 Microsemi Corporation. Company Proprietary Power Matters.TM 10
Slide 11: PLL and SERDES Radiation Update
PLL and SERDES Radiation Update © 2017 Microsemi Corporation. Company Proprietary Power Matters.TM 11
Slide 12: PLL
PLL PLL Single Event Functional Interrupt (SEFI) is defined by PLL loss of lock Heavy-Ion SEE Testing Results • PLL lost lock and self-recovers at LET < 65 MeV-cm2/mg • PLL lost lock and can be recovered by reset at LET = 65 MeV-cm2/mg • Lock loss < 100 us More testing is planned Cross Section
Slide 13: SERDES SEE Test and SEFI Auto-Recover
SERDES SEE Test and SEFI Auto-Recover Hardened 1. Controller in external master chip manages the testing system. 2. Configuration register in SERDES is SEE hardened but has upset. 3. When SERDES SEFI occurs, controller detects the event based on looped back data. 4. A command is sent to on-chip Core
Slide 14: SERDES SEFI Results
SERDES SEFI Results SERDES SEFI is defined by loss of link • Several signals were monitored • Loss of link is when returned data is invalid for 2+ consecutive cycles © 2017 Microsemi Corporation. Company Proprietary Power Matters.TM 14
Slide 15: SERDES Summary
SERDES Summary No DEVRST_N was required to recover link loss Most SEFI were self-recoverable • Others required reinitializing SERDES configuration registers using CoreABC Link loss was recoverable with duration in sub-millisecond range Plan for next testing: • Improve SERDES test design and
Slide 16: In-Flight Reprogramming―In-Beam Reprogramming Test
In-Flight Reprogramming―In-Beam Reprogramming Test © 2017 Microsemi Corporation. Company Proprietary Power Matters.TM 16
Slide 17: In-Beam RTG4 Reprogramming
In-Beam RTG4 Reprogramming FlashPro used by customers Off-Beam Reprogram Pass Fluence until Prog Fail Reprogram Functional Reprogram Attempts Reprogram Passed Reprogramming in beam often gets interrupted Fluence (Ion/cm2) Effective Flux Effective LET (Ion/cm2/s) No damage at LET ≤ 30.5 Run R
Slide 18: In-Beam Reprogramming Error
In-Beam Reprogramming Error Example: Run 24, Bit stream error programmer '87254' : Scan Chain... programmer '87254' : Scan Chain PASSED. programmer '87254' : Executing action PROGRAM programmer '87254' : EXPORT ISC_ENABLE_RESULT[32] = 00004404 programmer '87254' : EXPORT CRCERR: [1] = 0 programmer
Slide 19: In-Beam Reprogramming SEFI―Register Upset
In-Beam Reprogramming SEFI―Register Upset Run 25, Nominal, Tilt: 0 LET: 1.23, Fluence: 6.00E+05, Temperature: Room Run 27, Nominal, Tilt: 0 LET: 8.17, Fluence: 1.41E+06, Temperature: Room 0.38 1.4 0.385 1.4 0.36 1.2 0.365 1.2 0.34 1 0.345 1 Current (A) Voltage (V) Current (A) Voltage (V) 0.32 0.3 0.
Slide 20: In-Beam Reprogramming Soft SEFI―Cross Section and Error Rate
In-Beam Reprogramming Soft SEFI―Cross Section and Error Rate 1.0E-04 Cross Section (cm2) 1.0E-05 1.0E-06 GEO MIN Rate = 2.8 10-3 event/device/day 1.0E-07 0 5 10 15 20 25 30 35 LET (MeV-cm2/mg) © 2017 Microsemi Corporation. Company Proprietary Power Matters.TM 20
Slide 21: In-Flight Reprogramming Guidance
In-Flight Reprogramming Guidance Preliminary guidance • Highly unlikely that a destructive event will occur during programming in space • Probability of success for programming in GEO is estimated ~ 99% or higher • It is highly likely that in space, no ion will disrupt programming • If an ion stri
Slide 22: Prompt-Dose/Dose-Rate Testing
Prompt-Dose/Dose-Rate Testing Contact Microsemi for more information Ken O’Neill Director of Marketing, Space, and Aviation 408-643-6179 ken.oneill@microsemi.com Minh Nguyen Senior Marketing Manager, Space 408-643-6283 minh.u.nguyen@microsemi.com © 2017 Microsemi Corporation. Company Proprietary
Slide 23: RTG4 Radiation Summary
RTG4 Radiation Summary Total Ionizing Dose Stays within parametric limits > 125 Krad (Si) Single Event Latch-Up No failure at facility limit of 103 MeV-cm2/mg, 100°C Configuration Upset No failure at facility limit of 103 MeV-cm2/mg, 100°C Flip-Flop SEU 2.6E-12 errors/bit-day, GEO solar minimum, 1MH
Slide 24: Thank You
Thank You Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs,