Microsemi — Technical Presentation (June 2016)
49 slides from Microsemi's technical presentation, Jun 14, 2016
Slide 1: NEPP Independent Single Event Upset Testing of the Microsemi RTG4: Preliminary Data
NEPP Independent Single Event Upset Testing of the Microsemi RTG4: Preliminary Data Melanie Berg, AS&D in support of NASA/GSFC Melanie.D.Berg@NASA.gov Kenneth LaBel, NASA/GSFC Jonathan Pellish, NASA/GSFC Presented Presented by Melanie by Melanie BergBerg at NASA at the the NASA Electronics Electroni
Slide 2: Acronyms
Acronyms • Clock conditioning Circuit (CCC) • NASA Electronics Parts and Packaging (NEPP) • Combinatorial logic (CL) • Operational frequency (fs) • Dedicated Global I/O (DGBIO) • PLL: Phase locked loop • Design under analysis (DUA) • POR: Power on reset • Device under test (DUT) • Radiation Effects
Slide 3: Introduction
Introduction • This is a NASA Electronics Parts and Packaging (NEPP) independent investigation to determine the single event destructive and transient susceptibility of the Microsemi RTG4 device (DUT). • For evaluation: the DUT is configured to have various test structures that are geared to measure
Slide 4: Preliminary Investigation Objective for DUT Functional SEE Response
Preliminary Investigation Objective for DUT Functional SEE Response • The preliminary objective, of this study, is to analyze operational responses while the DUT is exposed to ionizing particles. • Specific analysis considerations: – Analyze flip-flop (DFF) behavior in simple designs such as shift r
Slide 5: FPGA SEU Categorization as Defined by NASA Goddard REAG
FPGA SEU Categorization as Defined by NASA Goddard REAG: SEU cross section: σSEU Design σSEU Configuration σSEU Functional logic SEFI σSEU σSEU Sequential and Combinatorial Global Routes logic (CL) in and Hidden data path Logic SEU Testing is required in order to characterize the σSEUs for each of F
Slide 6: RTG4 Radiation-Mitigated Architecture
RTG4 Radiation-Mitigated Architecture Figure is Courtesy of Microsemi Corporation. • Total-dose hardening of Flash cells. • Single-event hardening of registers, SRAM, multipliers, PLLs. Comprehensive radiation-mitigated architecture for signal processing applications Presented by Melanie Berg at the
Slide 7: Microsemi RTG4: Device Under Test (DUT) Details
Microsemi RTG4: Device Under Test (DUT) Details LUT: look up table. • The DUT : RT4G150-CG1657M. SRAM: sequential random access memory. DSP: digital signal processing. • We tested Rev B and Rev C devices. PLL: phase locked loop. • The DUT contains: DFFs are radiation – 158214 look up tables (4-input
Slide 8: DUT Preparation
DUT Preparation Top Side of DUT • NEPP has populated two Rev B and one populated Rev C boards with RT4G150-CG1657M devices. • The parts (DUTs) were thinned using mechanical etching via an Ultra Tec ASAP-1 device Ultra Tec preparation system. ASAP-1 • The parts have been successfully thinned to 70um
Slide 9: Challenges for Testing
Challenges for Testing TID: total ionizing dose • Software is new… place and route is not optimal yet. Hence, it is difficult to get high speed without manual placement. • We did not perform manual placement. • Microsemi reports that devices show TID tolerance up to 160Krads. – Although, when testin
Slide 10: Summary of Test Structures and Operation
Summary of Test Structures and Operation • Windowed Shift Registers (WSRs): – All designs contained four separate WSR chains. – Chains either had 0 inverters, 4 inverters, 8 inverters, or 16 inverters. – Resets were either synchronous or asynchronous. – Input data patterns varied: checkerboard, all
Slide 11: Windowed Shift Registers (WSRs): Test Structure
Windowed Shift Registers (WSRs): Test Structure Presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June13–16, 2016. 11
Slide 12: Windowed Shift Registers (WSRs)
Windowed Shift Registers (WSRs): Each DUT Contains 4 WSR Chains Chain0 4-bit Window Chain1 4-bit Window Tester Chain2 4-bit Window Chain3 4-bit Window Presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June13–16, 2016. 1
Slide 13: Microsemi RTG4 Clock Conditioning Circuit (CCC)
Microsemi RTG4 Clock Conditioning Circuit (CCC) FDDR: Double Data Rate Interface Control; SERDES: Serial-De-serializer; • CLKBUF: Hardened global route. Input POR: Power on reset; can only be a DGBIO pad. PLL: Phase locked loop; • CLKINT: Hardened global route. Input GBn: global network; can come fr
Slide 14: Asynchronous Assert Synchronous De-Assert Resets (AASD)
Asynchronous Assert Synchronous De- Assert Resets (AASD) • AASD is the traditional method of reset implementation in NASA driven systems. • This is a requirement for the protection of a mission in case of loss- of-clock. • Synchronization is performed prior to clock tree connection. Clock Tree Buffe
Slide 15: List of WSR Implementations: Design Variations on the Clock Path
List of WSR Implementations: Design Variations on the Clock Path • Clock input to the DUT is either a dedicated clock I/O (DGBIO) or a normal I/O. • All clocks are placed on a clock tree. The clock tree is either a CLKINT or a CLKBUF. • All DFF data inputs are either in a normal state or contain an
Slide 16: List of WSR Implementations: Design A
List of WSR Implementations: Design A: 4 clk 4 rst • Design has WSR0, WSR4, WSR8, WSR16 with 800 stages each. • All clocks are connected to CLKINT. Only WSR0 has a DGBIO. • Each WSR chain has it’s own synchronized reset. • Rev B used a mixture of AASD and pure synchronous resets. • Rev C used only p
Slide 17: List of WSR Implementations: Design B
List of WSR Implementations: Design B: 4 clk 4 rst FILTER • Design has WSR0, WSR4, WSR8, WSR16 with 800 stages each. • All clocks are connected to CLKINT. Only WSR0 has a DGBIO. • Each WSR chain has it’s own synchronized AASD reset. • SET Filter is active on every DFF in all WSR chains. • Only imple
Slide 18: List of WSR Implementations: Design C
List of WSR Implementations: Design C: 4 clk 4 rst Direct CLKBUF • Design has WSR0, WSR4, WSR8, WSR16 with 800 stages each. • All clocks are connected to CLKBUF. All WSR chains have a DGBIO. • Each WSR chain has it’s own synchronized AASD reset. • SET Filter is active on every DFF in all WSR chains.
Slide 19: List of WSR Implementations: Design D
List of WSR Implementations: Design D: Large shift register • 20,000 stage WSRs. • DUT has 4 chains of WSR0 (i.e., no inverters between DFF stages): Chain0, Chain1, Chain2, Chain3. • All clocks are connected to CLKINT. Only Chain0 has a DGBIO. • No resets are used. DGBIO Chain0 Clk and Reset Chain1,
Slide 20: List of WSR Implementations: Design E
List of WSR Implementations: Design E: Large shift register FILTER • 20,000 stage WSRs. • DUT has 4 chains of WSR0 (i.e., no inverters between DFF stages): Chain0, Chain1, Chain2, Chain3. • All clocks are connected to CLKINT. Only Chain0 has a DGBIO. • No resets are used. • SET Filter is active on e
Slide 21: List of WSR Implementations: Design F
List of WSR Implementations: Design F: Large shift register CCC • 20,000 stage WSRs. • DUT has 4 chains of WSR0 (i.e., no inverters between DFF stages): Chain0, Chain1, Chain2, Chain3. • All clocks are connected to output of the CCC block. • All clock inputs are directly connected to a DGBIO. • No r
Slide 22: Summary of WSR Designs Under Test
Summary of WSR Designs Under Test Design Design CLK I/O Pin Clock Reset Number of SET Filter Name Buffer Stages A 4 CLK 4 RST WSR0:DGBIO All All CLKINT 800 OFF Others: I/O CLKINT B 4 CLK 4 WSR0:DGBIO All All CLKINT 800 ON RSTFILTER Others: I/O CLKINT C 4 CLK 4 RST All DGBIO All All CLKINT 800 ON Dir
Slide 23: WSRs: Frequency of Operation and Data Patterns
WSRs: Frequency of Operation and Data Patterns • Halt Operation: – Data patterns: checkerboard, all 1’s, all 0’s. – Registers are loaded with a data pattern while beam is turned off. Beam is turned on while clocks are static (however, registers are still enabled). Beam is turned off and the tester r
Slide 24: Counter Arrays
Counter Arrays • DUT contains two sets of the following: – 200 8-bit counters – 200 8-bit snapshot registers • All counters and snapshot registers are connected to the same clock tree and RESET. • The clock tree is fed by the CLK input from the LCDT. • DUT CLK is connected to a DGBIO and a CLKBUF. •
Slide 25: Microsemi RTG4 Test Conditions
Microsemi RTG4 Test Conditions • Temperature range: Room temperature • Facility: Texas A&M. • Performed December 2015, March 2016, and May 2016. • NEPP Low Cost Digital Tester (LCDT) and custom DUT board.. • LET: 1.8 MeVcm2/mg to 20.6 MeVcm2/mg. Presented by Melanie Berg at the NASA Electronics Part
Slide 26: Block Diagram of RTG4 Test Environment
Block Diagram of RTG4 Test Environment LCDT DUT Presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June13–16, 2016. 26
Slide 27: Characterizing Single Event Upsets: Accelerated Radiation Testing and SEU Cross Sections
Characterizing Single Event Upsets (SEUs): Accelerated Radiation Testing and SEU Cross Sections SEU Cross Sections (σseu) characterize how many upsets will occur based on the number of ionizing particles to which the device is exposed. # errors σ seu = fluence Terminology: • Flux: Particles/(sec-cm2
Slide 28: Accelerated Test Results
Accelerated Test Results Presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June13–16, 2016. 28
Slide 29: Configuration
Configuration Presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June13–16, 2016. 29
Slide 30: Configuration Re-programmability
Configuration Re-programmability • During this test campaign, tests were only performed up to an LET of 20.6MeVcm2/mg. • Higher LETs will be used during future testing. • No re-programmability failures were observed up to an LET of 20.6MeVcm2/mg when within particle dose limits. Presented by Melanie
Slide 31: WSRs
WSRs Presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June13–16, 2016. 31
Slide 32: Halt Accelerated Tests
Halt Accelerated Tests • LET=20.6 MeV*cm2/mg the test fluence was 1.0e7 particles/cm2; and LET=5.0 MeV*cm2/mg the test fluence was 2.0e7 particles/cm2. • Designs are held in a static state because the clock is suspended. • Upsets are expected to come from a clock tree, reset tree, or an internal DFF
Slide 33: Halt Accelerated Tests: DFFs
Halt Accelerated Tests: DFFs • No internal DFF upsets were observed. • No SEUs were observed on any of the chains that were connected to a DGBIO and a CLKBUF pair. • SET filters did not make a difference. – This is as expected because data-path SETs cannot be captured (DFFs are not clocked). • All c
Slide 34: Rev B Reset Evaluation
Rev B Reset Evaluation: 4 clk 4 rst Synchronous Reset Driven Shift Registers: σSEU 1.00E-07 per LET WSR0 160MHz Checkerboard Pattern WSR4 160MHz Synchronous versus WSR8 160MHz AASD…Insignificant difference 1.00E-08 WSR0 100MHz between SEU cross-sections. σSEU (cm2/DFF) WSR4 100MHz WSR8 100MHz 1.00E-
Slide 35: Rev C: CLK RST FILTER versus LET at 100MHz
Rev C: 4 CLK 4 RST FILTER versus LET at 100MHz 7.00E-09 Add combinatorial logic, increase cross section. 6.00E-09 How and what you WSR16 Checkerboard test makes a big WSR8 Checkerboard 5.00E-09 difference! WSR4 Checkerboard SEU(cm /DFF) WSR0 Checkerboard 4.00E-09 WSR16 All 1's 2 WSR8 All 1's 3.00E-0
Slide 36: Comparing WSR Chains: With and Without Filter at LET 20.6
Comparing WSR Chains: 4 clk 4 rst with Filter and 4 clk 4 rst …100MHz with LET = 20.6MeVcm2/mg 3.50E-08 Clear improvement with use of SET filter with high LET. 3.00E-08 WSR16 4 clk 4 rst filter WSR8 4 clk 4 rst filter 2.50E-08 WSR4 4 clk 4 rst filter WSR0 4 clk 4 rst filter WSR16 4 clk 4 rst 2.00E-0
Slide 37: Clk rst Direct CLKBUF SEU Cross Sections versus Frequency
4 Clk 4 rst Direct CLKBUF SEU Cross Sections versus Frequency at LET = 20.6 MeVcm2/mg Data across LET was not able to be taken because of limited test time with this design. 8E-09 WSR16: Checkerboard WSR16 : All 1's 7E-09 WSR16 All 0's 6E-09 SEU (cm /DFF) WSR8: 4 checkerboard 5E-09 WSR8: All 1's 2 4
Slide 38: Comparing DUT Variations: Direct CLKBUF and/or SET Filter
Comparing 4 clk 4 rst DUT Variations: How much Better Is A Direct Connection to CLKBUF and/or A SET Filter? WSR16 at 100MHz LET=20.6 WSR0 at 100MHz LET=20.6 3.50E-08 Comparisons 3.50E-08 Comparisons 3.00E-08 3.00E-08 4 clk 4 rst direct clkbuf 4 clk 4 rst direct clkbuf 2.50E-08 2.50E-08 4 clk 4 rst F
Slide 39: Introducing Large WSRs (1)
Introducing Large WSRs (1): Comparison of WSR0 SEU Cross Sections at 100MHZ at LET = 20MeV*cm 2/mg 4.50E-09 Only design that contains PLL. PLL is unmitigated. 4.00E-09 3.50E-09 Large Shift Reg CCC SEU (cm /DFF) 3.00E-09 4 clk 4 rst Direct CLKBUF 2.50E-09 4 clk 4rst FILTER 2 2.00E-09 4 clk 4 rst 1.50
Slide 40: Introducing Large WSRs (2)
Introducing Large WSRs (2): Comparison of WSR0 SEU Cross Sections at 100MHZ at LET = 20MeV*cm2/mg • Checkerboard pattern: all designs have observable SEU cross-sections. • All 1’s: 4 clk 4 rst Direct CLKBUF and Large Shift Reg FILTER have negligible SEU cross-sections. • All 0’s: Only 4 clk 4 rst (n
Slide 41: WSR Accelerated Radiation Test Data Observations
WSR Accelerated Radiation Test Data Observations • SEUs can originate in clocks trees, reset trees (not with long shift- regs), and data paths. • In Rev C, resets are connected via the synchronous tree and reset SETs would require a clock edge capture. • WSR0s: – When only analyzing all 1’s or all 0
Slide 42: WSR Accelerated Radiation Test Data Observations
WSR Accelerated Radiation Test Data Observations • In some tests, WSR input pattern of All 1’s had greater SEU cross sections than WSR input pattern of checkerboard. – This only occurred with designs that used resets. Most likely the reset was the cause. – The use of resets in a synchronous design i
Slide 43: Counters
Counters Presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June13–16, 2016. 43
Slide 44: Rev C Counter Arrays
Rev C Counter Arrays • Counter SEU cross-sections Rev C Counter Arrays Single Bit σSEUs: are lower than the without SET Filter versus with SET Filter at corresponding (i.e., with filter 50MHz or without) WSRs with 3.0E-09 Counter WITHOUT SET Filter checkerboard. Counter WITH SET Filter – Only counte
Slide 45: Rev C versus Rev B Counter Arrays
Rev C versus Rev B Counter Arrays Rev B Counter Array Single Rev C Counter Arrays Single Bit σSEUs: Bit σSEUs at 50MHz without SET Filter versus with SET Filter at 50MHz 3.00E-09 3.0E-09 Counter WITHOUT SET Filter Counter without SET FILTER Counter WITH SET Filter 2.50E-09 2.5E-09 σSEU (cm2/DFF) σSE
Slide 46: NEPP: ProASIC3 Accelerated Heavy-ion Test Results
NEPP: ProASIC3 Accelerated Heavy-ion Test Results RTG4 shows an improvement over ProASIC3 in functional data path. Presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June13–16, 2016. 46
Slide 47: RTAX4000D and RTAX2000 WSRs at 80MHz with Checkerboard Pattern
RTAX4000D and RTAX2000 WSRs at 80MHz with Checkerboard Pattern 1.00E-06 RTAX4000D and RTAX2000 have better SEU performance than RTG4 (higher LETon-set; and 1.00E-07 slightly lower σSEUs); but not by much. 1.00E-08 Cross Section (cm /bit) (cm2/DFF) 2 1.00E-09 RTAX4000D RTAX4000DWSR8I WSR σSEU 8 1.00E
Slide 48: Future Work
Future Work • DUT Test structures: – Additional counter array tests (will try for higher frequencies). – Embedded SRAM (LSRAM and μSRAM). – I/O evaluation: CCC: Clock Conditioning Circuit • Multiprotocol 3.125Gbit SERDES. DSP: Digital signal processing • Space wire interface block. DDR: double data
Slide 49: Acknowledgements
Acknowledgements • Some of this work has been sponsored by the NASA Electronic Parts and Packaging (NEPP) Program and the Defense Threat Reduction Agency (DTRA). • NASA Goddard Radiation Effects and Analysis Group (REAG) for their technical assistance and support. REAG is led by Kenneth LaBel and Jo