Slide 1: MOS Capacitor (MOSCAP) Device Physics
MOS Capacitor (MOSCAP) Device Physics Reviewed 2025 © 2022-2025 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Statements regarding product
Slide 2: Copyright guidelines
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Slide 4: Device Physics Module Sequence
Device Physics Module Sequence 1. Semiconductor fundamentals & PN junction device physics - Energy band diagram, fermi-level, density of states, doping, PN junction 2. MOS Capacitor (MOSCAP) - MOS electrostatics, ideal CV, non-idealities, key parameter extractions 3. MOS Transistor (MOSFET) - Channe
Slide 5: Table of Contents
Table of Contents MOS Capacitor (MOSCAP) 1 Goals, objectives and target audience 2 Ideal MOSCAP – Accumulation – Depletion – Inversion 3 Threshold and Inversion Charge 4 MOS CV Characteristics 5 MOS CV Non-Idealities 6 Glossary 7 References 5
Slide 6: MOS Capacitor (MOSCAP) – goal and objectives
MOS Capacitor (MOSCAP) – goal and objectives Goal Objectives • Provide a foundational understanding of MOS • Illustrate the architecture and operations of capacitor and its electrical characteristics MOSCAP • Interpret and draw band-diagram for different material systems and operating conditions 6
Slide 7: Target Audience
Target Audience • Interns, NCGs (new college grads) and new employees in some technical roles need to understand these concepts Pro tip • Examples of critical target audience roles at Micron that utilize Everyone interviewing at Micron can these concepts use this presentation to prepare for – Device
Slide 8: Ideal MOSCAP
Ideal MOSCAP 8
Slide 9: MOSCAP
MOSCAP MOS stands for Metal Oxide Semiconductor, CAP stands for capacitor VG MOSCAP is a two-terminal device Metal (Gate): Al (aluminum) was used initially, and then poly-Si Metal (Gate) was being used heavily because of its ability to withstand high Oxide temperature, and recent trend is to reintro
Slide 10: MOSCAP
MOSCAP Why study MOSCAP? • The most used semiconductor device in industry is MOSFET (in both digital/analog) Schematic of a MOSFET device • In MOSFET current flow between source and drain can be controlled by controlling the OFF State ON State VG = 0 VG > 0 gate potential (with respect to body/sourc
Slide 11: Energy Band Diagram
Energy Band Diagram Energy band levels for three separate components of MOS, VG Vacuum level E0 qχSiO2 Metal (Gate) EC Oxide qχSi qФM Please see slide 13 for qФSi energy band diagram p-type Si parameter definitions EC Ef Ei Body Ef EV N-channel MOS (N-MOS) capacitor using a p-type Si bulk will be em
Slide 12: Ideal MOSCAP
Ideal MOSCAP VG 1. WF (Workfunction) Metal = WF Semiconductor (Silicon) 2. Oxide has no charges Metal (Gate) 3. No surface states at Oxide-Silicon interface Oxide 4. Oxide has infinite resistivity/perfect insulator (no current flow Semiconductor through the oxide throughout the operation) Body 12
Slide 13: Ideal MOS Band Diagram
E0 = Vacuum level For SiO2, Si Ideal MOS Band Diagram qχSiO2 = Electron affinity qχSiO2 ~ 0.95V Ef = Fermi level Eg ~ 9.0eV Metal Ox P-type Ei = Intrinsic Fermi level qФB ~ 3.1eV EC = Conduction band edge qχSiO2 ~ 0.95eV Vacuum level E0 EV = Valence band edge qχSi ~ 4.05V qχSiO2 Eg = Band gap qФM qФ
Slide 14: MOS Electrostatic with External Bias (Summary)
MOS Electrostatic with External Bias (Summary) Accumulation (VG < 0) Flat Band (VG = 0) Depletion (VG > 0) Inversion (VG > VT) q𝝋s EC q𝝋s VG Ei Ei Ei Ei 𝒒∅𝒃 Ref. energy level Ef Ef Ef q𝝋s Ef EV VG VG Electron energy, 𝐸 = −𝑒. 𝑉 Surface potential at Ox-Si interface, 𝜑𝑠 𝝋𝒔 < 0 𝝋𝒔 = 0V…
Slide 15: MOSCAP in Accumulation
tox VG 0V MOSCAP in Accumulation - Metal - Ox P-type - VG 1. Negative charges at metal can’t go through the oxide ρv Holes Charge neutrality, 2. The majority carriers at p-type Si will accumulate at surface 𝑄𝑀 + 𝑄𝑆𝑖 = 0 𝑄𝑆𝑖 = 𝑄𝐴𝑐𝑐 x ξ Electric field, 𝜌𝑣 𝑥 x ξ=න 𝑑𝑥 𝜀 Electric…
Slide 16: MOSCAP in Depletion
tox VG 0V MOSCAP in Depletion + Metal + Ox P-type VG + 1. Positive charges at metal can’t go through the oxide ρv Charge neutrality, 2. The majority carriers at p-type Si will get repelled (grounded) xd 𝑄𝑀 + 𝑄𝑆𝑖 = 0 𝑄𝑆𝑖 = 𝑄𝐷𝑒𝑝 x 3. Negative dopants ions will be Exposed acceptors…
Slide 17: MOSCAP in Inversion
tox VG + 0V MOSCAP in Inversion + + Metal + Ox P-type VG + + 1. As we keep increasing the VG, we keep increasing the depletion width to a maximum value (Xd,max) ρv Charge neutrality, 2. At this juncture, the surface is xd,max 𝑄𝑀 + 𝑄𝑆𝑖 = 0 𝑄𝑆𝑖 = 𝑄𝐼𝑛𝑣 + 𝑄𝐷𝑒𝑝 inverted to n-type Si x…
Slide 18: Surface Potential & Band Bending
Surface Potential & Band Bending Accumulation Depletion 𝜑𝑠 =2∅𝑏 Strong Inversion 𝝋𝒔 0 Threshold = Onset of strong inversion (channel is inverted from p-type to n-type, electron concentration at surface equals holes concentration at bulk) Convention: 𝝋𝒔 is positive when energy band bends down…
Slide 19: Surface Potential & Band Bending
Surface Potential & Band Bending Accumulation Depletion 𝜑𝑠 =2∅𝑏 Strong Inversion 𝝋𝒔 0 Threshold = Onset of strong inversion (channel is inverted from p-type to n-type, electron concentration at surface equals holes concentration at bulk) Convention: 𝝋𝒔 is positive when energy band bends down…
Slide 20: Inversion Charge
𝑄 ′ : charge per unit area 𝐶 ′ : capacitance per unit area Inversion Charge M: Metal Si: Silicon Ox: Oxide dielectric (SiO2) 𝑄𝑀 + 𝑄𝑆𝑖 = 0 Dep: Depletion (Silicon) Inv: Inversion 𝑉𝐺 : Potential At onset of strong inversion (threshold), 𝑉𝐺 : Gate potential 𝑉𝑂𝑥: Potential drop across…
Slide 21: Recap: Capacitor/Capacitance
Recap: Capacitor/Capacitance Parallel plate capacitance 𝐴 𝐶=𝜀 𝑡 Top electrode 𝜀 Insulator 𝐶′ = 𝐶 ′ ∶ capacitance per unit area 𝑡 Bottom electrode Question: What’s the equivalent/total capacitance of these configurations? 𝑽 𝑽 𝑽 𝑪′ 𝑪′ 𝑪′ 𝑪′ 𝑪′ 21
Slide 22: Recap: Capacitor/Capacitance
Recap: Capacitor/Capacitance Parallel plate capacitance 𝐴 𝐶=𝜀 𝑡 Top electrode 𝜀 Insulator 𝐶′ = 𝐶 ′ ∶ capacitance per unit area 𝑡 Bottom electrode Question: What’s the equivalent/total capacitance of these configurations? 𝑽 𝑽 𝑽 𝑪′ 1 1 1 ′ = + 𝐶𝑇𝑜𝑡𝑎𝑙 𝐶′ 𝐶′ 𝑪′ 𝑪′ 𝑪′ 𝑪 ′ 𝑪′…
Slide 23: CV Characteristics
CV Characteristics Metal AC small signal Oxide ∆𝑄 x 𝑉 ± ∆𝑉 𝑄 ± ∆𝑄 𝐶= ∆𝑉 p-sub ρv ±∆𝑄 xd xd,max x x x ′ 𝜀𝑆𝑖 ′ 𝜀𝑆𝑖 -qNA 𝐶𝐷𝑒𝑝 = 𝐶𝐷𝑒𝑝,𝑚𝑖𝑛 = ∓∆𝑄 𝑥𝑑 𝑥𝑑,𝑚𝑎𝑥 Accumulation Depletion Inversion 𝜀𝑜𝑥 1 1 1 𝜀𝑜𝑥 𝐶 ′ = 𝐶𝑜𝑥 ′ = = + 𝐶 ′ = 𝐶𝑜𝑥 ′ = 𝑡𝑂𝑥 𝐶′ ′ 𝐶𝑜𝑥 ′…
Slide 24: CV Characteristics
CV Characteristics Metal AC small signal Oxide ∆𝑄 x 𝑉 ± ∆𝑉 𝑄 ± ∆𝑄 𝐶= ∆𝑉 p-sub ρv ±∆𝑄 xd xd,max x x x ′ 𝜀𝑆𝑖 ′ 𝜀𝑆𝑖 -qNA 𝐶𝐷𝑒𝑝 = 𝐶𝐷𝑒𝑝,𝑚𝑖𝑛 = ∓∆𝑄 𝑥𝑑 𝑥𝑑,𝑚𝑎𝑥 Accumulation Depletion Inversion • If we sweep the ∆V (small signal) very fast (high 𝜀𝑜𝑥 1 1 1 𝜀𝑜𝑥 𝐶 ′ =…
Slide 25: Minority carrier response
Minority carrier response Metal AC small signal Oxide x p-sub 1 1 1 = + VG ′ 𝐶𝑚𝑖𝑛 ′ 𝐶𝑜𝑥 ′ 𝐶𝐷𝑒𝑝,𝑚𝑖𝑛 AC (small signal) 𝜀𝑆𝑖 DC ramp ′ 𝐶𝐷𝑒𝑝,𝑚𝑖𝑛 = 𝐂′ Accumulation 𝑥𝑑,𝑚𝑎𝑥 DC LF 𝑪′𝒎𝒊𝒏 HF t V 𝑉𝑇 𝜑𝑠 = 2𝜙𝑏 At very high frequency, there are no electrons to respond from…
Slide 26: Thermal Generation-Recombination Mechanism
26 Thermal Generation-Recombination Mechanism EC Trap state Ef EV • Thermal generation of electron-hole pair at depletion region and separated by depletion electric field • Thermal generation of electron-hole pair is a sluggish (slow) process • Trap states could assist thermal generation of electron
Slide 27: Deep Depletion
VG Too fast ramp / significant Deep Depletion change in DC gate voltage xd,max x -qNA C’ Accumulation Missing electrons t xdeep x 1 1 1 ′ 𝜀𝑆𝑖 = + 𝐶𝐷𝑒𝑝,𝑑𝑒𝑒𝑝 = -qNA 𝐶′ ′ 𝐶𝑜𝑥 ′ 𝐶𝐷𝑒𝑝, 𝑑𝑒𝑒𝑝 𝑥𝑑,𝑑𝑒𝑒𝑝 Charge neutrality, HF Inversion 𝑄𝑀 + 𝑄𝑆𝑖 = 0 Deep Depletion 𝑄𝑆𝑖 =…
Slide 28: HF Inversion vs Deep Depletion
HF Inversion vs Deep Depletion Charge Neutrality must be maintained at all time HF Inversion: |𝑄𝑀 | = |𝑄𝐼𝑛𝑣 + 𝑄𝐷𝑒𝑝 | • Inversion charge exist, but it can’t respond to fast-changing AC small signal • Electrons, minority carrier must be thermally generated, slower process than fast-changing…
Slide 29: Deep Depletion
VG Too fast ramp / significant Deep Depletion change in DC gate voltage xd,max x -qNA C’ Accumulation Missing electrons t xdeep x 1 1 1 ′ 𝜀𝑆𝑖 = ′ + ′ 𝐶𝐷𝑒𝑝,𝑑𝑒𝑒𝑝 = -qNA 𝐶′ 𝐶𝑜𝑥 𝐶𝐷𝑒𝑝, 𝑑𝑒𝑒𝑝 𝑥𝑑,𝑑𝑒𝑒𝑝 Charge neutrality, 𝑄𝑀 + 𝑄𝑆𝑖 = 0 Deep Depletion 𝑄𝑆𝑖 = 𝑄𝑖𝑛𝑣 +…
Slide 30: MOS Electrostatics and Charge Diagram Summary
MOS Electrostatics and Charge Diagram Summary Accumulation Depletion Inversion Deep Depletion EC EC Ei EC Ef Ei EV Ei Ef Ef EV EC EV Ei Ef EV ρv QM QM QM xd xd xd x x x x QM -qNA -qNA -qNA QS Missing electrons QM xdeep x -qNa 30
Slide 31: Temperature Dependence on HF CV
Temperature Dependence on HF CV Higher T C’ Accumulation EC T = 250°C Ef EV T = 100°C T = 30°C V • Higher temperature increases thermal carrier generation rate, i.e: higher intrinsic carrier concentration • Minority carrier responds to HF CV, approaches LF CV at very high temperature Question: What
Slide 32: Temperature Dependence on HF CV
Temperature Dependence on HF CV Higher T C’ Accumulation EC T = 250°C Ef EV T = 100°C T = 30°C V • Higher temperature increases thermal carrier generation rate, i.e: higher intrinsic carrier concentration • Minority carrier responds to HF CV, approaches LF CV at very high temperature Question: What
Slide 33: Parameter Extractions
ρv +∆𝑸 Parameter Extractions xd x x -qNA C’ Accumulation −∆𝑸 Accumulation Depletion ′ 𝐶𝐴𝑐𝑐 ➔ Provides 𝜀𝑜𝑥 1 1 1 information about tox 𝐶 ′ = 𝐶𝑜𝑥 ′ = = + 𝑡𝑜𝑥 𝐶′ ′ 𝐶𝑜𝑥 ′ 𝐶𝐷𝑒𝑝 ′ 1 1 1 𝐶𝑚𝑖𝑛 (HF CV) ➔ Provides ′ = ′ + ′ 𝐶𝑚𝑖𝑛 𝐶𝑜𝑥 𝐶𝐷𝑒𝑝,𝑚𝑖𝑛 information about doping…
Slide 34: Effect of Increased Substrate Doping
Effect of Increased Substrate Doping 2𝑞𝑁𝐴 𝜀𝑆 (2∅𝑏 ) 𝑉𝑇 = ′ + 2∅𝑏 Accumulation 𝐶𝑂𝑥 C’ ′ 𝜀𝑜𝑥 𝐶𝑜𝑥 = 𝑡𝑜𝑥 NA ↑ 1 1 1 ′ = ′ + ′ 𝐶𝑚𝑖𝑛 𝐶𝑜𝑥 𝐶𝐷𝑒𝑝,𝑚𝑖𝑛 V 𝑉𝑇 𝜑𝑠 = 2𝜙𝑏 ′ 𝜀𝑆𝑖 𝐶𝐷𝑒𝑝,𝑚𝑖𝑛 = 𝑥𝑑,𝑚𝑎𝑥 • NA ↑ ➔ V T ↑ ′ • Max depletion width reduces, 𝐶𝑚𝑖𝑛…
Slide 35: Effect of Increased Oxide Thickness
Effect of Increased Oxide Thickness 2𝑞𝑁𝐴 𝜀𝑆 (2∅𝑏 ) 𝑉𝑇 = ′ + 2∅𝑏 Accumulation 𝐶𝑂𝑥 C’ ′ 𝜀𝑜𝑥 𝐶𝑜𝑥 = 𝑡𝑜𝑥 1 1 1 tox ↑ ′ = ′ + ′ 𝐶𝑚𝑖𝑛 𝐶𝑜𝑥 𝐶𝐷𝑒𝑝,𝑚𝑖𝑛 V 𝑉𝑇 𝜑𝑠 = 2𝜙𝑏 • Max capacitance reduces due to lower oxide capacitance ′ • 𝐶𝑚𝑖𝑛 decreases (Si capacitance is in…
Slide 36: MOS CV Non-Idealities
MOS CV Non-Idealities 36
Slide 37: MOSCAP Non-Idealities
MOSCAP Non-Idealities Recall the assumptions for Ideal MOSCAP 1. WF (Workfunction) Metal = WF Semiconductor (Silicon) 2. Oxide has no charges 3. No surface states at Oxide-Silicon interface 4. Oxide has infinite resistivity/perfect insulator Let’s see the impact to MOSCAP with some non-idealities (#
Slide 38: Metal-Semiconductor Workfunction Difference
Metal-Semiconductor Workfunction Difference E0 qχSiO2 qФM qФBM qФBS qФSi EC Ei 𝑉𝐹𝐵 = ∅𝑀𝑆 = ∅𝑀 − ∅𝑆𝑖 = 0 Ef Eg Ef EV Assume oxide/interface charges = 0 Metal SiO2 Si MOS at equilibrium: Matched WF 38
Slide 39: Metal-Semiconductor Workfunction Difference
Metal-Semiconductor Workfunction Difference E0 qχSiO2 Si is already partially depleted even without gate bias ➔ lower VT Low WF qФM qФBS qФBM qФBS qФSi qФBM EC Ei EC Ef Ef Ef Ei EV qФMS Eg Ef EV ∅𝑀𝑆 < 0 Metal SiO2 Si Metal SiO2 Si MOS not “in contact” MOS at equilibrium 39
Slide 40: Non-Idealities: Workfunction Mismatch
Non-Idealities: Workfunction Mismatch Lower workfunction metal gate, negative ∅𝑀𝑆 𝑉𝑇 = 𝑉𝐹𝐵 + 𝑉𝑜𝑥 + 𝜑𝑠 𝑄𝐹 𝑄𝐼𝑡 𝑉𝐹𝐵 = ∅𝑀𝑆 − + 𝐶𝑜𝑥 𝐶𝑜𝑥 C’ Accumulation The capacitance value is uniquely determined by 𝜑𝑠 . Silicon capacitance is variable, but oxide capacitance is…
Slide 41: Metal-Semiconductor Workfunction Difference
Metal-Semiconductor Workfunction Difference E0 qχSiO2 Si is strongly accumulated without qФBM gate bias ➔ Higher VT High WF qФBS qФSi qФBS qФM qФBM EC Ei EC Ef EF Ei EF EV Eg qФMS EV Ef ∅𝑀𝑆 > 0 Metal SiO2 Si Metal SiO2 Si MOS not “in contact” MOS at equilibrium 41
Slide 42: Non-Idealities: Workfunction Mismatch
Non-Idealities: Workfunction Mismatch Higher workfunction metal gate, positive ∅𝑀𝑆 𝑉𝑇 = 𝑉𝐹𝐵 + 𝑉𝑜𝑥 + 𝜑𝑆𝑖 𝑄𝐹 𝑄𝐼𝑡 𝑉𝐹𝐵 = ∅𝑀𝑆 − + 𝐶𝑜𝑥 𝐶𝑜𝑥 C’ Accumulation The capacitance value is uniquely determined by 𝜑𝑠 . Silicon capacitance is variable, but oxide capacitance is…
Slide 43: Applications: WF Matching for MOS Gate
Applications: WF Matching for MOS Gate Example of N-MOS Band Diagrams with N+/P+ Poly-Si Gate at VG = 0V WF matching is crucial to achieve low threshold voltage, which Low VT High VT is crucial for fast switching and high performance (MOS based transistors) Surface is partially depleted w/o gate bia
Slide 44: Capacitor Voltage (CV) Non-Idealities
Capacitor Voltage (CV) Non-Idealities 1. Fixed Oxide Charges 2. Interface Traps 44
Slide 45: Non-Idealities: Fixed Oxide Charges
Non-Idealities: Fixed Oxide Charges 1. Typically, SiO2 is grown on Silicon surface SiO2 2. Transition region is non-ideal, SiOx ➔ Oxygen vacancies 3. Fixed oxide charges arises at Si/Oxide interface due to incomplete ++++++++++ SiOx oxidation 4. Fixed oxide charges are always positive Si Si + O 45
Slide 46: Non-Idealities: Oxide Charges
Non-Idealities: Oxide Charges Example: N-MOS threshold voltage 𝑄𝐹 𝑄𝐼𝑡 𝑉𝑇 = 𝑉𝐹𝐵 + 𝑉𝑜𝑥 + 𝜑𝑠 𝑉𝐹𝐵 = ∅𝑀𝑆 − + 𝐶𝑜𝑥 𝐶𝑜𝑥 Positive interface charges or fixed/oxide trapped charge will shift VT to more negative 46
Slide 47: Effect of Fixed Oxide Charges
Effect of Fixed Oxide Charges Metal QF +++++++++++++++++++ C’ Accumulation QF2 > QF1 > QF0 p-sub QF2 QF1 QF0 = 0 V 𝑉𝑇 𝜑𝑠 = 2𝜙𝑏 1. Fixed positive charges attracts electrons (negative charges) at Si interface 2. QF ↑➔ VT ↓ 3. Shift/translation/parallel shift of CV curve Question: What happens…
Slide 48: Effect of Fixed Oxide Charges
Effect of Fixed Oxide Charges Metal QF +++++++++++++++++++ C’ Accumulation QF2 > QF1 > QF0 p-sub QF2 QF1 QF0 = 0 V 𝑉𝑇 𝜑𝑠 = 2𝜙𝑏 1. Fixed positive charges attracts electrons (negative charges) at Si interface 2. QF ↑➔ VT ↓ 3. Shift/translation/parallel shift of CV curve Question: What happens…
Slide 49: Non-Idealities: Interface Trap Charges
Non-Idealities: Interface Trap Charges • Si is tetrahedrally bonded to 4 Si atoms in bulk Si, at interface Si lattice terminates abruptly • Interface trap formed when trivalent Si atom with an unsaturated/unpaired valence electron at the interface • Interface traps, density and charges are denoted b
Slide 50: Non-Idealities: Interface Trap Charges
Non-Idealities: Interface Trap Charges Ec • Interface traps are electrically active defects with an energy distribution Acceptor States throughout the Si bandgap Allowed • They act as generation/recombination centers and contribute to leakage Ei (midgap) energy states current, low frequency noise an
Slide 51: Non-Idealities: Interface Trap Charges
Non-Idealities: Interface Trap Charges Accumulation Depletion Inversion Ec Ec Ec “0” “0” “+” Ei Ei Ei “0” “0” Ef Ef Ef “0” EV EV “-” EV “0” Positively charged donors Neutral acceptors and donors Negatively charged acceptors • Difficult to accumulate holes • Difficult to invert 1. Fermi Level = Proba
Slide 52: Non-Idealities: Interface Trap Charges
Non-Idealities: Interface Trap Charges Metal C’ Accumulation Dit1 < Dit1 < Dit2 Qit xxxxxxxxxxxxxxx p-sub Dit1 = 0 Mid-gap V 𝑉𝑇 𝜑𝑠 = 2𝜙𝑏 1. Towards accumulation, positively charged interface states makes accumulation difficult 2. Towards inversion, negatively charged interface states make…
Slide 53: Question:
53 Question: If a MOS capacitor (MOSCAP) is sluggish and unable to respond effectively to HF-CV measurements, how can it still be utilized in advanced high-speed logic chips and processors? Answer in next slide -> 53
Slide 54: CV: MOSCAP vs MOSFET (Transistor)
CV: MOSCAP vs MOSFET (Transistor) MOSCAP MOSFET Metal Metal AC Oxide Oxide n+ n+ p-sub p-sub C’ Accumulation LF C’ Accumulation LF/HF HF v v In actual operations, the drain potential is forward biased which will drain the electrons, but the source side still can supply electrons to the channel ➔ Swi
Slide 55: Glossary
Glossary Micron
Slide 56: Glossary
Glossary Term or acronym Definition/description Accumulation A condition in MOSCAP where the majority carriers accumulate at the surface due to the applied gate potential Band Gap The energy difference between the conduction band edge (EC) and the valence band edge (EV) in a semiconductor. It determ
Slide 57: Glossary
Glossary Term or acronym Definition/description Gate The metal electrode used to control the electric field and potential applied to the semiconductor body. This control influences the behavior of the majority carriers within the MOSCAP structure. Gate bias The voltage applied to the gate terminal o
Slide 58: References
References Micron
Slide 59: Reference
Reference 1. Fundamental of Modern VLSI Devices, Yuan Taur and Tak H. Ning 2. Modern Semiconductor Devices for Integrated Circuits, Chenming Hu 3. Semiconductor Fundamentals, Robert F. Pierret 4. Semiconductor Physics and Devices, Donald Neamen 5. Physics of Semiconductor Devices, Simon Sze 59
Slide 60: © 2022–2025 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject
© 2022–2025 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Statements regarding products, including statements regarding product features,