Slide 1: Andes Technology Corp. Investor Conference Report
Andes Technology Corp. Investor Conference Report
Slide 2: Safe Harbor Notice
Safe Harbor Notice Except for the historical information contained herein, the matters addressed in this presentation are forward-looking statements that involve certain risks and uncertainties that could cause actual results to differ materially, including but not limited to weather, impact of comp
Slide 3: Table of Contents
Table of Contents 01 Company Overview 02 Operation Results 03 Product Applications 04 New Products and Ecosystems 05 Concluding Remarks 3
Slide 4: Company Overview
Company Overview http://www.andestech.com
Slide 5: Andes Highlights
Andes Highlights • Founded in March 2005 in Hsinchu Science Park, Taiwan, ROC. • Well-established high technology IPO company • Over 370 people; 80% are engineers. • TSMC OIP Award “Partner of the Year” for New IP (2015) • Founding Premier membership in the RISC-V International Association (RISC-V F
Slide 6: Business Status Overview
Business Status Overview ❖ 300+ commercial licensees ◼ Geographically distributed in Taiwan, China, Korea, Japan, Europe, and USA Andes- ◼ 600+ license agreements signed Embedded SoC ❖ AndeSight™ IDE: ◼ 24,000+ installations IP / EDA Design Service / Foundries ❖ Eco-system: ◼ 500+ partners Developme
Slide 7: Operation Results
Operation Results http://www.andestech.com
Slide 8: 4Q22 Revenue Analysis
4Q22 Revenue Analysis YoY QoQ +15 % +14.2 % (NT$ thousands) 8
Slide 9: 22 Q1-Q4 Revenue Analysis
22 Q1-Q4 Revenue Analysis YoY +13.7 % (NT$ thousands) 9
Slide 10: 22 Q1-Q4 Top 10 Customers Analysis by Revenue
22 Q1-Q4 Top 10 Customers Analysis by Revenue (NT$ thousands) 10
Slide 11: 4Q22 Royalty Analysis
4Q22 Royalty Analysis QoQ YoY -15% -17.8 % (NT$ thousands) 11
Slide 12: 22 Q1-Q4 Royalty Analysis
22 Q1-Q4 Royalty Analysis YoY -1.7 % (NT$ thousands) 12
Slide 13: 22 Q1-Q4 Top 10 Royalty Contributors by Application
22 Q1-Q4 Top 10 Royalty Contributors Analysis by Application (NT$ thousands) 13
Slide 14: 22 Q1-Q4 Revenue Analysis by Payment Model
22 Q1-Q4 Revenue Analysis by Payment Model 14
Slide 15: 22 Q1-Q4 Revenue Analysis by Region
22 Q1-Q4 Revenue Analysis by Region 15
Slide 16: 22 Q1-Q4 Revenue Analysis by Product
22 Q1-Q4 Revenue Analysis by Product 16
Slide 17: 4Q22 Revenue Analysis - RISC-V
4Q22 Revenue Analysis - RISC-V (NT$ thousands) 17
Slide 18: Product Applications
Product Applications http://www.andestech.com
Slide 19: V5 Adoptions: From MCU to Datacenters
V5 Adoptions: From MCU to Datacenters ❖Edge to Cloud ADAS Datacenter/server AI accelerators AIoT SSD: enterprise (& consumer) Blockchain 5G macro/small cells FPGA MCU Multimedia Security Wireless (BT/WiFi) ❖40nm to 3nm 5G Macro ❖Many in AI 19
Slide 20: Andes RISC-V Cores Adopted in SoC
Andes RISC-V Cores Adopted in SoC o single core ooooo oooooooooooooooooooo…oooooooooooooooooooo 2-8 cores ooo oooooooooooooooooooo…oooooooooooooooooooo oooooooooooooooooooo…oooooooooooooooooooo oooooooooooooooooooo…oooooooooooooooooooo oooooooo oooooooooooooooooooo…oooooooooooooooooooo oooooooo oooo
Slide 21: New Products and Ecosystems
New Products and Ecosystems http://www.andestech.com
Slide 22: Andes RISC-V Product Roadmap
Andes RISC-V Product Roadmap RV32/RV64 Vector Ext. Superscalar Out of Order A25MP 27-Series: 45-Series: 60-Series: Cache-Coherent 1-4 Cores AX25MP Vector Ext. Dual Issue > 2.5 GHz MemBoost Vector Ext. > 2x per-GHz MemBoost performance of NX27V Linux with A25 A27/AX27 N45/NX45/D45 45-Series FPU/DSP A
Slide 23: AX45 Can Do More (vs. 64bit A-series)
AX45 Can Do More (vs. 64bit A-series) ◼ A53 ◼ AX45 ⚫ 8-stage In-Order Dual Issue ⚫ 8-stage In-Order Dual Issue ⚫ Widely adopted by industries ⚫ Performance is better! in many applications • Coremark/MHz: 1.35x • Dhrystone/MHz: 1.42x 23
Slide 24: Target Applications for 27, 45, 60-Series
Target Applications for 27, 45, 60-Series ◼ AI/Deep Learning ◼ Video Surveillance ◼ AR/VR ◼ 5G ◼ ADAS ◼ Networking ◼ V2X (Vehicle to Everything) ◼ IVI (In-Vehicle-Infotainment) ◼ Storage Metaverse, HPC and more… 24
Slide 25: The Andes AX60 Processor Series
The Andes AX60 Processor Series ◼ A new generation of AndesCoreTM ⚫ Advanced Performance 13-stage Out-of-Order Superscalar Multicore ⚫ Latest RISC-V Architecture ⚫ Supported by Andes Long-term Roadmap – AX65 as the first member of the AX60 series – More products based on the AX60 micro-architecture
Slide 26: AndesCore AX65: 1st Member of AX60-Series
AndesCore AX65: 1st Member of AX60-Series ◼ 64-bit, RV64GCBK B1 F1 F2 D1 D2 D3 I1 I2 E1 E2 E3 E4 ◼ 8-core Multiprocessor ALU WB x3 issue, ◼ 13-stage OoO Pipeline batch, fetch, decode, rename, register +br & misc WB x1 align & buffer dispatch memory WB x2 ◼ 128-entry Reorder Buffer (ROB) read floatin
Slide 27: Andes is Driving Innovations in Automotive
Andes is Driving Innovations in Automotive with Industry’s 1st RISC-V ISO 26262 Fully Compliant Core, N25F-SE In-Cabin Radar CMOS Sensor Radar Host Subsystem Controller N25F-SE N25F-SE Radio Memory Peripheral Auto TDDI Auto MCU Auto Storage Subject to change without notice Copyright© 2021-2023 Andes
Slide 28: Thank You
Thank You http://www.andestech.com +886-3-5726533 28