Slide 1: CEVA-XC5 / CEVA-XC323
CEVA-XC5 / CEVA-XC323 Enabling Low Power Communications in Machine to Machine multi-mode endpoints
Slide 2: Introducing CEVA-XC5 / CEVA-XC323
Introducing CEVA-XC5 / CEVA-XC323 Low power communication DSPs designed to address the multi- mode connectivity requirements of M2M 70% Lower dynamic Latest generation of highly popular CEVA-XC vector processor family, power with already more than 30 licensees and tens of millions of devices consump
Slide 3: M2M Market Trends
M2M Market Trends Today industrial smart meters dominate the M2M market By 2018, the consumer market will surpass industrial Includes connected cars and appliances By 2020, 20% of M2M devices will use cellular technology in multiple segments Connected cars emergency Wearalone smartwatches Smart mete
Slide 4: M2M/IoT Communications Challenges
M2M/IoT Communications Challenges Key Challenges Existing Solutions Flexibility HW centric modems Many standards, some still under development Can’t be upgraded to track standards evolution and Specifications are not finalized and will require updates country variants and remote upgrades in the fi
Slide 5: CEVA-XC DSP Roadmap
CEVA-XC DSP Roadmap Vector DSP for M2M and Cellular UE LTE-A Cat9-12, Features Multimode UE XC4500 LTE Cat-1-4, 11n/11ah, LTE Cat-0/Cat-M, Multimode M2M GNSS, 11n/11ah, 15.4g XC164 CEVA-X2S XC5 XC323 XC4210 LTE CAT4 & Multimode UE Performance Previous Generation New Generation CEVA Proprietary Infor
Slide 6: CEVA-XC5/XC323 Architecture Highlights
CEVA-XC5/XC323 Architecture Highlights DSP Core Features Memory MSS and Subsystem Features & Connectivity 8-way unrestricted VLIW 4-way set associative non-blocking program Vector units with 16/32 MACs per cycle cache Dedicated communication ISA Powerful DMAs for instruction and data multi-core and
Slide 7: CEVA-XC5/XC323 Core Highlights
CEVA-XC5/XC323 Core Highlights Highly powerful communication processor Incorporates typical DSP capabilities with advanced vector processing units CEVA -XC5 performs 16 MAC per cycle CEVA -XC323 performs 32 MAC per cycle 8-way unrestricted VLIW Up to three vector units Up to four general units High
Slide 8: CEVA-XC5/XC323 Memory Subsystem
CEVA-XC5/XC323 Memory Subsystem Smooth Integration into Target SoCs AXI master and slave system buses Supports Low Power Interface protocol APB3 interface for slow devices Program cache Reduces internal program memory size DMA controller Background data transfers, de-interleaving Full Debug support
Slide 9: CEVA-XC5/XC323 Power Scaling Unit
CEVA-XC5/XC323 Power Scaling Unit PSU supports multiple clock sources: DSP Core Internal power unit manages the clock automatically High-level of granularity allows clocks shut-down for each block Memory subsystem Data and Program L1 Memories Emulation & Debug modules PSU supports multiple voltage d
Slide 10: Addressing Global M2M/IoT Connectivity
CEVA-XC5/XC323 Addressing Global M2M/IoT Connectivity CEVA Proprietary Information 10
Slide 11: Thank You
Thank You For more information, visit www.ceva-dsp.com/M2M