Andes Technology Corp. · TWSE:6533
Andes Technology — Q2 2023 Earnings Presentation
47 slides from Andes Technology's earnings presentation, Aug 17, 2023
Slide 1: Andes Technology Corp. Investor Conference Report
Andes Technology Corp. Investor Conference Report
Slide 2: Safe Harbor Notice
Safe Harbor Notice Except for the historical information contained herein, the matters addressed in this presentation are forward-looking statements that involve certain risks and uncertainties that could cause actual results to differ materially, including but not limited to weather, impact of comp
Slide 3: Table of Contents
Table of Contents 01 Company Overview 02 Operation Results 03 Product Applications 04 New Products and Ecosystems 05 Concluding Remarks 3
Slide 4: Company Overview
Company Overview http://www.andestech.com
Slide 5: Andes Highlights
Andes Highlights • Founded in March 2005 in Hsinchu Science Park, Taiwan, ROC. • Well-established high technology IPO company • Over 400 people; 80% are engineers. • TSMC OIP Award “Partner of the Year” for New IP (2015) • Founding Premier membership in the RISC-V International Association (RISC-V F
Slide 6: Business Status Overview
Business Status Overview ❖ 300+ commercial licensees ◼ Geographically distributed in Taiwan, China, Korea, Japan, Europe, and USA Andes- ◼ 600+ license agreements signed Embedded SoC ❖ AndeSight™ IDE: ◼ 25,000+ installations IP / EDA Design Service / Foundries ❖ Eco-system: ◼ 500+ partners Developme
Slide 7: Operation Results
Operation Results http://www.andestech.com
Slide 8: 2Q23 Revenue Analysis
2Q23 Revenue Analysis QoQ YoY -20.4 % +27.8 % (NT$ thousands) 8
Slide 9: 1H23 Revenue Analysis
1H23 Revenue Analysis YoY +15.1 % (NT$ thousands) 9
Slide 10: 1H23 Top 10 Customers Analysis by Revenue
1H23 Top 10 Customers Analysis by Revenue (NT$ thousands) 10
Slide 11: 2Q23 Royalty Analysis
2Q23 Royalty Analysis QoQ YoY -9.2 % -19.3 % (NT$ thousands) 11
Slide 12: 1H23 Royalty Analysis
1H23 Royalty Analysis YoY -18.6 % (NT$ thousands) 12
Slide 13: 1H23 Top 10 Royalty Contributors Analysis by Application
1H23 Top 10 Royalty Contributors Analysis by Application (NT$ thousands) 13
Slide 14: 1H23 Revenue Analysis by Payment Model
1H23 Revenue Analysis by Payment Model 14
Slide 15: 1H23 Revenue Analysis by Region
1H23 Revenue Analysis by Region 15
Slide 16: 1H23 Revenue Analysis by Product
1H23 Revenue Analysis by Product 16
Slide 17: 2Q23 Revenue Analysis - RISC-V
2Q23 Revenue Analysis - RISC-V (NT$ thousands) 17
Slide 18: Historical Revenue Analysis
Historical Revenue Analysis (NT$) License Royalty 18
Slide 19: 1H23 Consolidated Gross Margin
1H23 Consolidated Gross Margin (NT$ thousands) 19
Slide 20: 2Q23 Consolidated Operating Expenses
2Q23 Consolidated Operating Expenses QoQ YoY +15.8 % +48.3 % (NT$ thousands) 20
Slide 21: 1H23 Consolidated Operating Expenses
1H23 Consolidated Operating Expenses YoY +40.9 % (NT$ thousands) 21
Slide 22: 1H23 Consolidated Operating Income (Loss)
1H23 Consolidated Operating Income (Loss) YoY -% (NT$ thousands) 22
Slide 23: 1H23 Consolidated Net Income
1H23 Consolidated Net Income YoY -% (NT$ thousands) 23
Slide 24: 1H23 Consolidated EPS
1H23 Consolidated EPS YoY -5.79 $ (NT$) 24
Slide 25: Product Applications
Product Applications http://www.andestech.com
Slide 26: Andes RISC-V Cores Adopted in SoC
Andes RISC-V Cores Adopted in SoC o single core ooooo oooooooooooooooooooo…oooooooooooooooooooo 2-8 cores ooo oooooooooooooooooooo…oooooooooooooooooooo oooooooooooooooooooo…oooooooooooooooooooo oooooooooooooooooooo…oooooooooooooooooooo oooooooo oooooooooooooooooooo…oooooooooooooooooooo oooooooo oooo
Slide 27: Andes RISC-V Powering Rich Applications
Andes RISC-V Powering Rich Applications Mobile Cloud AI Space N25F, N45 D25F, D45, AX25MP, AX45MP Endpoints. Edge. Cloud. Space. Secure, control, compute, communicate, position Accelerate, accelerate, accelerate NX27V, AX25, AX27, AX45MP, N25F AX45MPV N25F, N45, AX45MP N25F, A25, A45MP, AX45MP Subje
Slide 28: MTIA: Meta Training and Inference Accelerator
MTIA: Meta Training and Inference Accelerator ◼ ISCA 2023 paper, “MTIA: First Generation Silicon Targeting Meta’s Recommendation Systems” ◼ Proc-A/B: Andes AX25-V100, an early version of the popular NX27V ◼ Custom extensions: for new interfaces, instructions and registers ◼ Performs quite well on lo
Slide 29: New Products and Ecosystems
New Products and Ecosystems http://www.andestech.com
Slide 30: Andes RISC-V Product Roadmap
Andes RISC-V Product Roadmap RV32/RV64 Vector Ext. Superscalar Out of Order A25MP 27-Series: 45-Series: 60-Series: Cache-Coherent 1-4 Cores AX25MP Vector Ext. Dual Issue > 2.5 GHz MemBoost Vector Ext. > 2x per-GHz MemBoost performance of NX27V Linux with A25 A27/AX27 N45/NX45/D45 45-Series FPU/DSP A
Slide 31: AndesCore AX65 OOO Application Processor
AndesCore™ AX65 OOO Application Processor ⚫ 13-stage 4-way 64-bit OOO processor B1 F1 F2 D1 D2 D3 I1 I2 E1 E2 E3 E4 ⚫ RVA22+ profile ALU WB x3 issue, +br & misc WB x1 ⚫ Multicore cluster up to 8 cores batch, fetch, decode, rename, register align & buffer dispatch memory WB x2 read ⚫ 8 Execution Pipe
Slide 32: Roadmap for the AX60 Series
Roadmap for the AX60 Series AX67 RVA24 and most performant AX66 AX65 Multi-cluster AX63 Balanced Power-optimized Efficient Mid-range Extended AX60 Series: 13-stage OOO Linux MP Subject to change without notice copyright © 2021-2023 Andes Technology Taking Mainstream 32
Slide 33: AX45MPV Multicore Cluster
AX45MPV Multicore Cluster ◼ At multicore cluster level: ⚫ Up to 8 cores ⚫ CM/L2$ subsystem – 128KB to 8MB, 64B line, 16-way – Multi-cycle support for high-density SRAMs – I/D prefetch, up to 64 outstanding requests ⚫ AXI Bus Interfaces up to 512 bits SPP ◼ Scalar Unit: RV64GCBP ⚫ 8-stage In-order du
Slide 34: AX45MPV: 1024-bit Vector Processor
AX45MPV: 1024-bit Vector Processor ◼ RISC-V Vector Extension (RVV v1.0) F1 F2 ID II EX MM LX WB ⚫ data format: int8~64, fp16~64; int4, bf16 ⚫ VLEN/DLEN: 128~1024 bits, 1:1 or 2:1 ratio ⚫ Up to 6 DLEN results per cycle ◼ Efficient support needed for tight coupling with HWE 1. Data exchange performanc
Slide 35: Andes is Driving Innovations in Automotive
Andes is Driving Innovations in Automotive with Industry’s 1st RISC-V ISO 26262 Fully Compliant Core, N25F-SE In-Cabin Radar CMOS Sensor Radar Host Subsystem Controller N25F-SE N25F-SE Radio Memory Peripheral Auto TDDI Auto MCU Auto Storage Subject to change without notice Copyright© 2021-2023 Andes
Slide 36: AndesCore RISC-V Functional Safety Roadmap
AndesCore™ RISC-V Functional Safety Roadmap High Performance Mission Critical 60-Series 13-stage, OoO D45-SE Computing Power 4-issue Mainstream 8-stage Processing Dual-issue ASIL-D Compliant (planning) ASIL-D Compliant D25F-SE ASIL-B Supported Low Power N25F-SE 5-stage IP: Q4, 2023 & Security 5-stag
Slide 37: N25F-SE, D25F-SE 5-Stage, ASIL-B Full Compliant
N25F-SE, D25F-SE 5-Stage, ASIL-B Full Compliant ◼ CPU Core ⚫ 5-stage, in-order, single-issue architecture ⚫ RISC-V RV32 GCB[P]* ISA, with Andes Extensions – D25F-SE with the RVP (SIMD/DSP) instruction extension – RVB bit-manipulation instructions for cryptography, … applications ⚫ AndeStar™ V5 32-bi
Slide 38: AndesCore N25F-SE Certified by ISO 26262
AndesCore™ N25F-SE Certified by ISO 26262 ◼ “The product has been approved in compliance with ASIL B requirements” ◼ ISO 26262 Edition 2018, parts: ⚫ ISO 26262-2:2018 ⚫ ISO 26262-4:2018* ⚫ ISO 26262-5:2018 ⚫ ISO 26262-8:2018 ⚫ ISO 26262-9:2018 ◼ Certification Body ⚫ SGS-TÜ V Saar GmbH ⚫ SGS-TÜ V Saa
Slide 39: D45-SE 8-Stage, Dual-Issue, up to ASIL-D
D45-SE 8-Stage, Dual-Issue, up to ASIL-D ◼ CPU Core ⚫ 8-stage, in-order, superscalar, dual-issue most instruction pairs ⚫ RISC-V RV32 GCBP* support, Andes Extensions ⚫ AndeStar™ V5 32-bit architecture ◼ Memory Subsystem ⚫ Instruction and data cache, up to 64KB ⚫ Instruction and data local memory, up
Slide 40: D23: Compact Controller for IoT/MCU/ECU
D23: Compact Controller for IoT/MCU/ECU ◼ 3-stage, limited dual-issue (optional) >1000 PMU Debug Trace Interrupts ◼ ISA extensions: ⚫ Base: RV32 I/E-MAC + B + Zce CLIC WFI / WFE Debug & Trace I/F ⚫ Advanced: FD + P + K + CMO 3-stage uCore, ePMP/sPMP/PMA Timer ◼ Privilege modes: M, S, U DSP FPU ACE ◼
Slide 41: D23: Compact Controller for IoT/MCU/ECU
D23: Compact Controller for IoT/MCU/ECU ◼ Memory subsystem: ⚫ Caches: ➢ Config: RISC-V Code Size Benchmarks • Icache only: ifetch IMAC + V5 IMABC + V5 IMABZce + • RO-cache (Read-Only): ifetch and load ISA IMAC (N22) (N25F) V5 (D23) • I/D caches: ifetch, load and store SPEC CPU 2,840 2,360 -16.9% 2,3
Slide 42: Security System Architecture for D23 (D23-SE)
Security System Architecture for D23 (D23-SE) • Create multiple zones protection by PMP/sPMP • REEs (Rich Execution Environment) • TEEs (Trusted Execution Environment) • IOPMP for IO protection REE TEE … FuSaEE Supervisor Mode Secure Monitor Machine Secure Boot Mode Andes RISC-V Cores ie D23 (D23-SE
Slide 43: Taking RISC-V Mainstream
Subject to change without notice Copyright© 2021-2023 Andes Technology Taking RISC-V® Mainstream 43
Slide 44: AndesAIRE AnDLA I350
AndesAIRE™ AnDLA™ I350 • Andes Deep Learning Accelerator (AnDLA™) AnDLA™ I350 • High performance-efficient deep learning accelerator for edge and end-point inference • General Matrix Scalable and multi-DLA DMA Multiply • Cooperate with AndesCore™ full series (22/23/25/27/45/65) • Accelerating for mo
Slide 45: Taking RISC-V Mainstream
Subject to change without notice Copyright© 2021-2023 Andes Technology Taking RISC-V® Mainstream 45
Slide 46: Taking RISC-V Mainstream
Subject to change without notice Copyright© 2021-2023 Andes Technology Taking RISC-V® Mainstream 46
Slide 47: Thank You
Thank You http://www.andestech.com +886-3-5726533 47