Slide 1: Hybrid Memory Cube Webinar July 2017
Hybrid Memory Cube Webinar July 2017 Stephan von Appen, Sr. Marketing Manager EMEA Mikko Hotti, FAE Specialist for HMC ©2016 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to ©2017 change without notice. All information is provided on an “AS IS”
Slide 2: Agenda
Agenda Stephan von Appen Mikko Hotti Sr. Marketing Manager EMEA FAE, HMC Lead for EMEA svonappen@micron.com mhotti@micron.com HMC Introduction and Status Technical Overview – The Memory Wall – Technical Collateral – What is the Hybrid Memory Cube – HMC Architectural Overview – Enabling Technologies
Slide 3: Hybrid Memory Cube Introduction and Status
Hybrid Memory Cube Introduction and Status Stephan von Appen, Sr. Marketing Manager Compute & Networking Business Unit July 2017 ©2017 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS
Slide 4: System Memory Bandwidth Gap
System Memory Bandwidth Gap MEMORY SYSTEMS ARE NOT SCALING AND DRIVE EXPONENTIAL COMPLEXITY DDR4 4-6 Memory Channels 284 Pins Per DIMM GB/s Up to 85GB/s 90 12 Speed Bins 6+ yrs to Standardize DDR3 75 3-4 Memory Channels 240 Pins Per DIMM Up to 59.7GB/s 60 5 Speed Bins DDR2 2 Memory Channels 45 Up to
Slide 5: The Memory Wall
The Memory Wall • WE STARTED TALKING ABOUT THE MEMORY WALL IN THE ‘90S – Evolutionary standards do NOT address The Memory Wall – Bandwidth AND power must be addressed • SYSTEM POWER LIMITS CONSTRAIN PERFORMANCE; PERFORMANCE CAN GROW IF POWER IS ADDRESSED • THE HYBRID MEMORY CUBE (HMC) IS A SOLUTION
Slide 6: Hybrid Memory Cube
Hybrid Memory Cube Hybrid – Stack of advanced DRAM plus logic – Combined into a single advanced BGA package – Serially attached to host via 15Gb/s SERDES lanes Memory – Current designs are DRAM-based memory Cube – Combines logic and DRAM layers into a performance optimized, 3D package leveragi
Slide 7: Hybrid Memory Cube
Hybrid Memory Cube Micron Innovation Unprecedented Performance We’ve combined fast logic process technology and advanced HMC provides a revolutionary performance enriching DRAM designs to create an entirely new category we’re calling next-generation networking and computing platforms Hybrid Memory C
Slide 8: Enabling Technologies
Enabling Technologies Abstracted Memory Through-Silicon Via (TSV) Management Assembly Memory Vaults Versus DRAM Arrays Innovative Design & Process Flow • Significantly improved bandwidth, quality and • Incorporation of thousands of TSV sites per die reliability versus traditional DRAM technologies r
Slide 9: Where does this fit?
Where does this fit? Primarily – Networking HMC’s impressive 160 GB/s bandwidth boosts networking systems’ capabilities to match line speed performance in the face of ever-increasing global demand for mobility and the impact of cloud services – High Performance Compute HMC’s high bandwidth, lo
Slide 10: Leading with New Innovations: HMC
Leading with New Innovations: HMC Revolutionary Approach to Break Through the “Memory Wall” Unparalleled Performance Evolutionary DRAM roadmaps hit limitations Provides 15X the bandwidth of a of bandwidth and power efficiency DDR3 module Micron introduces a new class of memory: Uses 70% less
Slide 11: HMC in Mass Production
HMC in Mass Production HMC SR-15 (Gen2) 31x31mm 1mm 4-Link Package pitch – 160GB/s Bandwidth 896 balls – 10Gbs, 12.5Gbs, 15Gbs SerDes – 31mm x31mm 4 link package – 2GB density Commercial Update – Production volume available now 2GB 4 DRAM die – Over 3 Mio cubes shipped to date – +250 leads to da
Slide 12: HMC Design Wins, Examples
*) incl MCDRAM HMC Design Wins, Examples South Africa’s MeerKAT array uses advanced Micron memory to explore deep space © 2017 Micron Technology, Inc. | Micron Confidential | July 11, 2017
Slide 13: Networking Example - 400Gb/s Buffering
Networking Example - 400Gb/s Buffering DDR4 Parameter DDR4-2400 72 # of Memory Devices [48 x16 & 24 x4 (ECC)] Network Total # of Pins 1,896 Processor Host PHY+ Memory 49W Power Memory Surface Area 8,532mm2 HMC HMC-15G-SR Parameter 4 Links @ 12.5Gb/s HMC System Level Savings # of Memory Devices 1 Tot
Slide 14: HMCC, Hybrid Memory Cube Consortium
HMCC, Hybrid Memory Cube Consortium http://www.hybridmemorycube.org/ Hybrid Memory Cube Consortium (HMCC) 8 Developers and 150+ Adopters HMCC Consortium Specifications Rev 1.0: >2,700 downloads since May’13 Rev 2.0: >2,600 downloads since Nov’14 OpenHMC Controller (Open Source) >7500* website access
Slide 15: Altera HMC Support
Altera HMC Support Stratix V Arria 10 Stratix 10 HMC 15G-SR Capable HMC Gen2 Controller IP Contact Intel Development Kit PSG for more Stratix V FPGA User Guide information Industry First 4 x FPGA Total HMC Demo! Reference Design Available 1 x HMC Device Now Singe FPGA “Master” 2013 2015 2017 © 2017
Slide 16: Altera Arria 10
Altera Arria 10 COMPREHENSIVE PRODUCTION HMC SUPPORT Arria 10 HMC IP – Supports HMC Specification 1.1 2 FMC slots Development Kit – High quality, internally developed HMC controller IP Reference Design – Fast simulation support, real time error statistics, Micron HMC HMC Controller IP Core hardwar
Slide 17: Xilinx Now Offering HMC IP
Xilinx Now Offering HMC IP Benefit Details • 240 Gb/s bandwidth per HMC link (Gen2, full duplex, x16 lanes) Excellent Performance • 85% reduced board space Fully HMC Gen2 Compliant Optimized & Verified Ultrascale & Ultrascale+ Controller IP • AXI Memory-Mapped interface Flexible & Parameterizable Co
Slide 18: VCU110
VCU110 400+ GBPS AND 28 GBPS BACKPLANE DEVELOPMENT Features Micron HMC – 4 CPF4 Optical Interfaces – 28 Gbps Backplane Interface – 20 GTY Interlaken Interface – 2 FMC HPC Interfaces – Micron HMC – Dual 512MB Quad-SPI flash – Micron 576Mb x18 RLDRAM 3 – Micron 576Mb x36 RLDRAM 3 © 2017 Micron Techn
Slide 19: OpenHMC
OpenHMC OPEN SOURCE HMC CONTROLLER Developed by the Computer Architecture Group (CAG) at the University of Heidelberg – Configurable – Vendor-agnostic – AXI-4 compliant – Flexible data-widths/lane widths and clock speeds depending on area requirements – Test environment to evaluate capabilities –
Slide 20: Micron Advanced Computing Solutions
Micron Advanced Computing Solutions Hardware • FPGA modules, boards, and systems targeted at HPC applications, all of which integrate the latest memory technologies from Micron technology • Fully-integrated solution Firmware & Software • Host drivers (Linux), APIs, etc.. • Memory controllers, PCIe i
Slide 21: Hardware Overview
Hardware Overview AC-Series: FPGA Compute Modules AC-505: 8GB DDR3 SODIMM, Kintex 7 AC-506: 8GB DDR3 SODIMM, Stratix V AC-510: 4GB HMC, Kintex Ultrascale AC-520: 2GB HMC, DDR4, Arria 10 (Q1 17) EX-Series: Backplanes for AC-Series EX-700: 6 AC Modules EX-750: 4 AC Modules SB-Series: Single Board HMC
Slide 22: Up to 6 Modules Populated on a Single PCIe Board
Up to 6 Modules Populated on a Single PCIe Board © 2017 Micron Technology, Inc. | Micron Confidential | July 11, 2017
Slide 23: Hardware Roadmap
Hardware Roadmap AC-520 AC-511 AC-521 AC-512 Modules • Arria 10 • VU7P • Stratix 10 • Xilinx • HMC • HMC • HMC • HMC • DDR4 • DDR4 • DDR4 • DDR4 SB-851 SB-852 SB-803 Single-board Computers • Virtex UltraScale+ • Virtex UltraScale+ • Stratix 10 • VU7P / VU9P • VU7P / VU9P • HMC • HMC or DDR4 • 2 x 2G
Slide 24: HMC Plug-and-Play System
HMC Plug-and-Play System Low power, small code size, Xilinx or Altera FPGA Mini-desktop PC built-in test & verification solutions Micron HMC Controller IP Fully HMC specification 1.1 compliant & validated/tested – Complete development system = Controller, Linux, Pico Framework, all hardware – Docu
Slide 25: HMC Technical Collateral
HMC Technical Collateral
Slide 26: HMC Technical Collateral
HMC Technical Collateral All HMC technical documents can be found from Micron.com using HMC as the search keyword HMC Datasheet and User Guide available without NDA, however Micron.com account is needed Documentation & Tools Status HMC Datasheet NOW HMC User Guide NOW Power Calculator Spreadshee
Slide 27: HMC Architecture Overview
HMC Architecture Overview
Slide 28: Hybrid Memory Cube
Hybrid Memory Cube TSV, HETEROGENEOUS SILICON LAYERS AND ADVANCED PACKAGING Memory Density 4H = 2GB Memory Bandwidth Wide Bus 160GB/s Logic Layer Processor High-Speed Link Bandwidth Serial Links 4x(16x2)x15Gbps = 240GB/s 10, 12.5, 15Gbps © 2017 Micron Technology, Inc. | Micron Confidential | July 11
Slide 29: HMC Step By Step - Lane
HMC Step By Step - Lane A lane is a single transceiver i.e. a TX and an RX combined Transmitter differential pair and serializer + Receiver differential pair and de- serializer Together, often referred to as a SERDES or Transceiver © 2017 Micron Technology, Inc. | Micron Confidential | July 11
Slide 30: HMC Step By Step - Link
HMC Step By Step - Link A Link is defined as a collection of 16 HMC Host Transceiver pairs (SERDES Tx and Rx) which are used to send and receive data TX 16 Tx RX A ½ link is therefore simply a collection of 8 Transceiver pairs (SERDES Tx and Rx) which are used to send and receive data RX 16 Rx T
Slide 31: HMC Step By Step - Quadrant
HMC Step By Step - Quadrant A Quadrant is defined as a single link (16 transceiver pairs), four vault controllers and four Memory Interface Quadrant 0 Quadrant 1 Controllers All Links can access all Quadrants using the internal HMC Crossbar Switch for “remote” quadrants Quadrant 2 Quadrant 3 © 2
Slide 32: HMC Step By Step - Vault
HMC Step By Step - Vault Every vault is functionally independent from every other vault Access and control of each vault is through a local vault controller in the logic A vault supports from 16 Byte to 128 Byte data transfers per access There are 16 vaults per HMC © 2017 Micron Technology,
Slide 33: HMC Step By Step - Link Controller Interface
HMC Step By Step - Link Controller Interface Logic Base HMC Host Memory Memory Memory Interface Interface Interface TX 16 TX RX Vault Vault Vault Controller Controller Controller RX 16 RX TX Crossbar Switch Each Link has 16 Lanes (RX/TX pairs) Link Interface Link Interface Link Interface Link Interf
Slide 34: HMC Single Link Bandwidth
HMC Single Link Bandwidth As one link has 16 Rx and 16 Tx transceivers the maximum bandwidth for a single link is 60GB/s Max single link BW Link 1 when 15Gb/s lane 16 Rx speed is used = Link 0 HMC Link 2 16 x 2 x 15Gb/s = 60GB/s 16 Tx Link 3 © 2017 Micron Technology, Inc. | Micron Confidential | J
Slide 35: HMC Summary
HMC Summary A lane is a single transceiver i.e. a TX and an RX combined. Supports data rates of 10.0 Gb/s , 12.5 Gb/s , and 15.0 Gb/s (duplex) A Link is defined as a collection of 16 Transceiver pairs (SERDES Tx and Rx) which are used to send and receive data A ½ link is a collection of 8 Tran
Slide 36: HMC Topologies and Chaining
HMC Topologies and Chaining
Slide 37: HMC System Topologies
HMC System Topologies Near Memory – All links between host and HMC – Maximum BW per GB density Far Memory Applications – HMC links connect to host or other cubes – HPC/Server – Links form networks of cubes – Networking – Scalable to meet system requirements – Test Equipment – Graphics © 2017 M
Slide 38: HMC Topologies
HMC Topologies CHAINED, STAR, OR HOST TO CUBE MULTI-HOST OPERATION SUPPORTED HOST LINK L0 L2 LINK HOST HMC 0 LINK L1 L3 LINK 1 © 2017 Micron Technology, Inc. | Micron Confidential | July 11, 2017
Slide 39: HMC Protocol
HMC Protocol
Slide 40: Packet Layout
Packet Layout Host issues requests and the HMC issues responses Packets are comprised of 128-bit (16B) FLITs Each Packet Contains 64b (8B) Header and 64b (8B) Tail 127 64 63 0 FLIT 1 Data1 Header FLIT 2 Data1 FLIT n-1 Data1 FLIT n Tail Data1 Note 1: Data only included in packet if applicable t
Slide 41: Protocol Overhead
Protocol Overhead 127 64 63 0 FLIT 1 Data Header FLIT 2 Data FLIT n-1 Data FLIT n Tail Data Protocol Access size # of FLITs Overhead 16B 2 50% 32B 3 33% 48B 4 25% 64B 5 20% 80B 6 17% 96B 7 14% 112B 8 13% 128B 9 11% © 2017 Micron Technology, Inc. | Micron Confidential | July 11, 2017
Slide 42: Which SERDES rate makes the most sense?
Which SERDES rate makes the most sense? Example: – 90GB of Bandwidth needed – 64B packets 108GB of SERDES BW required due to Protocol overhead. Options: – 3 links @ 10Gbps BW = (32 * 3 * 10G)/8 = 120GB – 3 links @ 12.5Gbps BW = (32 * 3 * 12.5G)/8 = 150GB – 2 links @ 15Gbps BW = (32 * 2 * 15G)/
Slide 43: End-to-End Error Protection
End-to-End Error Protection © 2017 Micron Technology, Inc. | Micron Confidential | July 11, 2017
Slide 44: Sideband Access
Sideband Access HMC includes support for JTAG and I2C – Both can be used to program and monitor configuration and status registers JTAG – Test access port compliant to IEEE 1149.1-2001 & 1149.6 – Including boundary scan support – Operates up to 100 MHz clock I2C – Operates up to 400Kb/s (fast
Slide 45: Contacts
Contacts
Slide 46: Micron HMC EMEA Distributor Contacts
Micron HMC EMEA Distributor Contacts Arrow Martin Neumueller – mneumueller@arroweurope.com Szabolcs Bondor – sbondor@arroweurope.com Avnet Joerg Siemers – joerg.siemers@avnet.eu Eran Peer – eran.peer@avnet.eu Eastronics Danny Kastenberg – danny.kastenberg@easx.co.il Galit Cohen-Sofer – galit.cohen-s
Slide 47: Slide 47