Slide 1: Andes Technology Corp. Investor Conference Report
Andes Technology Corp. Investor Conference Report Ted Chang Spokesperson Mar. 04, 2024
Slide 2: Safe Harbor Notice
Safe Harbor Notice Except for the historical information contained herein, the matters addressed in this presentation are forward-looking statements that involve certain risks and uncertainties that could cause actual results to differ materially, including but not limited to weather, impact of comp
Slide 3: Report Topics
Report Topics ⚫ Andes Company Introduction ⚫ The Financial & Operation Status ⚫ The Key Applications & The Trend ⚫ The R&D Power for The Future 3
Slide 4: Andes Company Introduction
Andes Company Introduction Andes Highlights • Founded in March 2005 in Hsinchu Science Park, Taiwan, ROC. • Well-established high technology IPO company • Over 500 people; 80% are engineers. • TSMC OIP Award “Partner of the Year” for New IP (2015) • Founding Premier membership in the RISC-V Internat
Slide 5: Andes Technology Corporation Quick Facts
Andes Technology Corporation Quick Facts on Andes 19 Years 500+ 400+ Customers 14Bn+ SoC Pureplay CPU vendor Employee , > 80% R&D Licensing AndesCore Total Customer Shipment 2023 Operation Result Revenue $ Growth License $ Growth Royalty $ Growth SoC Shipping Q’ty 1.04 Bn, NT$ 18.3% YoY -1.2% YoY 2.
Slide 6: The Financial & Operation Status
The Financial & Operation Status 6
Slide 7: 4Q23 Revenue Analysis
4Q23 Revenue Analysis YoY QoQ YoY +31.2 % +64 % +13.5 % (NTD ’000) (NTD ’000) Taking RISC-V® Mainstream 7
Slide 8: 2023 Q1-Q4 Revenue Analysis by Application
2023 Q1-Q4 Revenue Analysis by Application Taking RISC-V® Mainstream 8
Slide 9: 2021 to 2023 Revenue Analysis by Application
2021 to 2023 Revenue Analysis by Application (NTD ’000) Taking RISC-V® Mainstream 9
Slide 10: 4Q23 Royalty Analysis
4Q23 Royalty Analysis YoY QoQ YoY +32.3 % +8.1 % -1.2 % (NTD ’000) (NTD ’000) Taking RISC-V® Mainstream 10
Slide 11: 2023 Q1-Q4 Revenue Analysis by Business Model
2023 Q1-Q4 Revenue Analysis by Business Model Taking RISC-V® Mainstream 11
Slide 12: 2023 Q1-Q4 Revenue Analysis by Region
2023 Q1-Q4 Revenue Analysis by Region Taking RISC-V® Mainstream 12
Slide 13: 4Q23 Revenue Analysis - RISC-V
4Q23 Revenue Analysis - RISC-V (NTD ’000) Taking RISC-V® Mainstream 13
Slide 14: Historical License Revenue Analysis
Historical License Revenue Analysis (NTD ’000) License Revenue Taking RISC-V® Mainstream 14
Slide 15: Historical Royalty Revenue Analysis
Historical Royalty Revenue Analysis (NTD ’000) Royalty Revenue Taking RISC-V® Mainstream 15
Slide 16: The Key Applications & The Trend
The Key Applications & The Trend 16
Slide 17: The Key Applications & The Trend
The Key Applications & The Trend RISC-V will capture RISC-V will command 28% of the RISC-V-based AI SoCs will grow 73.6% 10% of the Automotive market by 2025 IoT market by 2025 CAGR to 25B units and $291B in revenue Counterpoint, Sept 2021 Counterpoint, Sept 2021 by 2027 Semico Research, Dec 2021 Ta
Slide 18: RISC-V growth momentum Led by Industrial Leader
• RISC-V growth momentum Led by Industrial Leader Leading Semiconductor Industry Players Join RISC-V crypto core is qualified to ASIL-D for NSITEXE Selects ImperasDV for Automotive Forces to Accelerate RISC-V automotive designs Quality RISC-V Processor Functional Design Aug. 2023 Jan. 2020 Verificat
Slide 19: Andes is Supporting RISC-V for Automobiles
Andes is Supporting RISC-V for Automobiles Since founded in March 2005, 2024 Andes Technology is working step-by-step on 2022 RISC-V for ISO 26262 Functional Safety AndesCore 2020 D25F-SE to be AndesCore Released 2017 Andes N25F-SE Certified • A series of Andes for ISO 26262 Functional Safety Develo
Slide 20: AndesCore for Automotive Electronics
AndesCore for Automotive Electronics ◼ Supporting a Wide Variety of Functional Safety Applications: ⚫ Dashboard display, in-car monitoring, keyless entry, lighting control, tire pressure monitoring, vision ADAS, microcontroller and many more ◼ Developers using AndesCore Functional Safety Processors
Slide 21: Andes FUSA Roadmap
Andes FUSA Roadmap High Performance Mission Critical AX6X-SE 13-stage Computing Power D45-SE OoO, 4-issue Mainstream 8-stage Low Power Processing Dual-issue & Security ASIL-D Compliant D25F-SE D23-SE N25F-SE 5-stage ASIL-D Compliant ASIL-B Supported 3-stage 5-stage Single-issue Single-issue Single-i
Slide 22: Andes Automotive Ecosystem
Andes Automotive Ecosystem ◼ Co-working with global leading suppliers in the automotive industry ◼ Andes and ecosystem partners jointly deliver the trusted RISC-V automotive solutions to designers complying with the standard of functional safety ISO 26262 ◼ Partner Ecosystem Catalogs Security Safety
Slide 23: RISC-V for Datacenter & Cloud
RISC-V for Datacenter & Cloud RISC-V offers unique Custom computing for Achieve your Opportunity for AI and performance and accelerators other emerging power targets workloads RISC-V CPU core market will grow 115% CAGR, capturing > 14% of all CPU cores by 2025 23
Slide 24: Andes RISC-V Processors to Fit Your AI
Andes RISC-V Processors to Fit Your AI Data center >100 TOPS Automotive Mobile AR/VR >10 TOPS Surveillance • ADAS, HDR • > 10 cameras >1 TOPS Smart Home • Face unlock • Bokeh Andes V-Series Avatar >1 GOPS Smart Camera • (RV64GCPV) • Gesture recognition • Intelligent HMI • SLAM AnDLA • Barge-in • Hig
Slide 25: MTIA: Meta Training/Inference Accelerator
MTIA: Meta Training/Inference Accelerator ◼ ISCA 2023 paper, “MTIA: First Generation Silicon Targeting Meta’s Recommendation Systems” ◼ Proc-A/B: AX25-V100, an early version of the popular NX27V ◼ Custom extensions: for new interfaces, instructions and registers ◼ Performs quite well on low and medi
Slide 26: Edge AI With Analog In-Memory Computing
Edge AI With Analog In-Memory Computing ◼ TetraMem Analog In-Memory-Computing MX200 (RRAM-based) ◼ 8-bit 256x256 (64K) MAC Engines, >30 TOPS/W performance ◼ ML core operators (conv, gemm) processed in NPU ◼ Remaining operations processed in RISC-V Vector processors and control CPU AXI Bus "Thousands
Slide 27: Endpoint AI
Endpoint AI ◼ Renesas R9A06G150 Voice-Control ASSP ◼With 100MHz DSP-capable D25F processor ◼ML-based voice recognition gets >50% speedup by using P-extension ◼ Spacetouch SPV60 Intelligent audio processor ⚫ High performance for customer development ◆ 100 GOPS NPU for noise reduction, echo cancellati
Slide 28: AndesAIRE: Andes AI Runs Everywhere
AndesAIRE : Andes AI Runs Everywhere ◼ HW/SW Solutions for AI from the Edge to the Cloud NN models AndesAIRE NN SDK AndeSight IDE AndesAIRE NNPilot • GCC/LLVM Toolchains Pruning, Quantization, Optimization, Evaluation • Build, debug, profile Generated C code template Generated NN models • Analysis a
Slide 29: AndesAIRE - Andes AI Runs Everywhere
AndesAIRE - Andes AI Runs Everywhere Smart Camera Smart Sensor Smart Home Appliance AIoT / tinyML Robotics Wearable 29
Slide 30: The R&D Power for The Future
The R&D Power for The Future 30
Slide 31: Andes RISC-V CPU Cores
Andes RISC-V CPU Cores AX60 Series AX65 AX66 AX6X-SE A72~A78; 13-stage OOO Linux MP N1/V1/X1 Categories Power-efficient Mid-range Extended FUSA 45 Series AX45MPV A53/55, R52/ N45, NX45 D45 D45-SE 8-stage Superscalar A45(MP), AX45(MP) R82, M7 27 Series NX27V A27(L2), AX27(L2) A5/7/35 5-stage MemBoost
Slide 32: RISC-V Continues to Rapidly Grow
RISC-V Continues to Rapidly ⚫ RISE: RISC-V Software Ecosystem, a project under LF Europe ⚫ To accelerate the development of RISC-V open source SW ⚫ Led by industry leaders ⚫ Areas to focus over time: ⚫ Compilers & Toolchains ⚫ Language Runtimes ⚫ System Libraries ⚫ Debug & Profiling Tools ⚫ Simulato
Slide 33: Andes Partners and RISC-V Ecosystem
Andes Partners and RISC-V Ecosystem AI tools, SW Security and IP DSP, Audio and Vision RTOS Development tools 33
Slide 34: Thank you
Thank you