Andes Technology Corp. · TWSE:6533
Andes Technology — Andes RISC-V CON Webinar 2020
29 slides from Andes Technology's conference presentation, Aug 27, 2020
Slide 1: RISC-V & SoC Architecture Exploration for AI & ML Many-core Compute Arrays
RISC-V & SoC Architecture Exploration for AI & ML Many-core Compute Arrays John Min Director of NA Field Application Engineering
Slide 2: Agenda
Agenda Andes Overview RISC-V & RVV (RISC-V Vector Extension) Overview Multicore Architectures Andes Custom Extension (ACE) Introduction Andes VPU (Vector Processing Unit) Microarchitecture Andes NX27V Vector Processor Development Tools Summary Andes RISC-V CON Webinar 2
Slide 3: At A Glance
At A Glance Who We Are RISC-V Founding Established CPU Pure-play CPU IP Company Premier Member Public Company Major Open-Source Running Task Groups Contributor/Maintainer Quick Facts 15 200+ 80% USA Netherlands France Beijing Korea years old Licensees R&D Israel Japan Shanghai company Worldwide empl
Slide 4: Andes V5 Architecture for All Levels of Computing
Andes V5 Architecture for All Levels of Computing AndeStar™ V5 Computing Domain Specific Architecture Device RV32/64 Andes Extension N/D-series Leading PPA Unlock RISC-V’s potential of DSA N22 N(X)25 D25… microcontroller A-series High performance and Define custom instruction to A(X)25 A(X)27 A(X)45
Slide 5: V5 Adoptions: From MCU to Datacenters
V5 Adoptions: From MCU to Datacenters Edge to Cloud: ADAS Datacenter AI accelerators AIoT SSD: enterprise (& consumer) Blockchain 5G macro/small cells FPGA MCU Multimedia Security Wireless (BT/WiFi) 5G Macro 1 to 1000+ core 40nm to 7nm Many in AI Andes RISC-V CON Webina
Slide 6: RISC-V & RVV Overview
RISC-V & RVV Overview Andes RISC-V CON Webinar 6
Slide 7: CRAY-1
CRAY-1 From Wiki: … the first supercomputer to successfully implement a vector processor design in 1975 … improve the performance of math operations by arranging memory and registers to quickly perform a single operation on a large set of data 64-bit Vector Processor@80MHz Source: CRAY-1 Wiki
Slide 8: Applications of Vector Processors
Applications of Vector Processors Computation Kernels (Matrix Multiply, FFT, Sort) Cryptography (RSA, DES/IDEA, SHA/MD5) Machine/Deep Learning, AR/VR Multimedia Processing (Graphics, Image, Video) Networking (memcpy, memset) Scientific Computing (Modeling and Analysis) All of these task
Slide 9: Multi-core Architectures
Multi-core Architectures Andes RISC-V CON Webinar 9
Slide 10: Threads?
Threads? Single Thread applications are disappearing Even simple tasks can be spawned to multiple tasks Web browser used to be single threaded…But now… Now Chrome takes 16 tasks Where PowerPoit is 1 task Breaking up independent tasks to accelerate performance Network requests Image r
Slide 11: The Compute Engine
The Compute Engine 1. Find the processor to that meets compute requirement Andes RISC-V CON Webinar 11
Slide 12: Parallel Compute Engines
Parallel Compute Engines 1. Find the processor to that meets compute requirement 2. Start Scaling up cores to meet parallel performance Andes RISC-V CON Webinar 12
Slide 13: Adding Compute
Adding Compute 1. Find the processor to that meets compute requirement 2. Start Scaling up cores to meet parallel performance Problem: Bus Bandwidth Andes RISC-V CON Webinar 13
Slide 14: Solving Data Delivery
Solving Data Delivery 1. Duplicate Clusters 2. Bring data close to compute engines 3. Proximity data – optimize data locality 4. Reduce bandwidth/contention Andes RISC-V CON Webinar 14
Slide 15: Optimized Multicore
Optimized Multicore 1. Reusing clusters minimize RISK 2. Easier to Debug 3. Easier to Program 4. Easier Migration of Tasks Andes RISC-V CON Webinar 15
Slide 16: Extending CPU Performance
Extending CPU Performance Andes RISC-V CON Webinar 16
Slide 17: Andes VPU
Andes VPU Fetch Decode Execute Memory Retire More Integer Data Except. Execution IFU Cache Handling Unit GPR Scalar VPU FPU V I Vector Q Andes RISC-V CON Webinar 17
Slide 18: NX27V Speedups
NX27V Speedups Functions Speedup1 F32 basic mathematical functions 19X RGB CNN functions 18X Depthwise CNN functions 18X Pointwise CNN functions 21X F32 filtering functions 19X Q7 filtering functions 39X F32 32x32x32 matrix multiplication 57X Note 1: Compared to pure C scalar code compiled with high
Slide 19: ACE and Accelerating Access
ACE and Accelerating Access Andes RISC-V CON Webinar 19
Slide 20: Adding Custom Instructions
Adding Custom Instructions IF II EX MM WB • RISC-V compliant 25-bit GPR Insn. ALU Data • ACR can be arbitrarily wide Branch Interrupt , Stall • Multiple ACMs Baseline GPR Load/Store • Automated RISC-V to ACE CPU signals ACR Vec Decode Decode User-written Execute Insn. Logic Auto-generated ACE Engine
Slide 21: ACE for Performance Efficiency
ACE for Performance Efficiency High speedup: Obvious results of defining instructions to match computation Energy reduction: No ACE: N instructions going thru fetch, decode, execute, retire N * (fetch + decode + retire) + N*execute With ACE: only 1 instruction fetch, decode, retire 1 *
Slide 22: Accelerating Memory Access
Accelerating Memory Access IF II EX MM WB • 25-bit for ACE instructions GP • OpCode, constant, registers, Insn. ALU R memories Data Branch Interrupt • User-defined flexibility , Stall • ACR can be arbitrarily wide GPR Load/Store Baseline • Multiple ACMs ACR • Automated RISC-V to ACE Decode Vec signa
Slide 23: Implementing Arbitrated Shared SRAM using ACE
Implementing Arbitrated Shared SRAM using ACE ACE=> Custom LD/ST Instructions with optional Local Register or GPR I$ BIU DLM ACM ACM=> Memory Access Core 0 ACE ACP System Periphery Bus Arbitration Control Bus SRAM ACM Core 1 ACE I$ BIU DLM ACP ACP => Optional Priority and ACK Andes RISC-V CON Webina
Slide 24: Controlling External Accelerators
Controlling External Accelerators AndesCore Ports + ACP ACE Engine ACP ACP ACP ACP Registers Memory ACP ACP Co-processor GPR ACR ACM ACP Co-processor (Host) Co-processor (Host) Co-processor (Host) SRAM Co-processor (Host) Customer (Host) Accclerator System Memory Andes RISC-V CON Webinar 24
Slide 25: Development Tools
Development Tools Andes RISC-V CON Webinar 25
Slide 26: Development Tools
Development Tools Standard tools in AndeSight™ IDE: AndeSim: Near-cycle accurate simulator Compiler (intrinsic functions and inline assembly) Assembler Debugger and ICE Computation library Advanced tools: AI compiler support thru LLVM AndesClarity pipeline visualizer and analyzer
Slide 27: Clarity: Pipeline View
Clarity: Pipeline View Andes RISC-V CON Webinar #Information subject to change w/o notice 27
Slide 28: Summary
Summary Flexible Architecture allows optimal Multi-core Performance optimization is critical to effectively process tasks Power savings by exploiting locality and using ACE ACE provides efficient data movement and expansion Advanced Software tools like AndesClarity for performance optimiza
Slide 29: Thank you!
Thank you!