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ASE Demonstrates CPO that Improves Energy Efficiency for AI applications
SUNNYVALE, Calif., April 01, 2025--Advanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711), today announced that it has demonstrated a co-packaged optics (CPO) device that mounts multiple optical engines (OE) directly onto a substrate, enabling <5pJ/bit power consumption and significant bandwidth increases. With today’s processing power requirements being extremely amplified by AI pervasion, there is unprecedented demand for bandwidth
About this update from Ase Technology Holding Co., Ltd.
[{"type":"text","content":"SUNNYVALE, Calif., April 01, 2025--(BUSINESS WIRE)--Advanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711), today announced that it has demonstrated a co-packaged optics (CPO) device that mounts multiple optical engines (OE) directly onto a substrate, enabling <5pJ/bit power consumption and significant bandwidth increases. With today’s processing power requirements being extremely amplified by AI pervasion, there is unprecedented demand for bandwidth that must be addressed. ASE’s new configuration enables crucial on-package energy efficiency and bandwidth expansion while addressing further data center challenges by delivering improvement related to latency, data throughput, and scalability.","length":765,"tagName":"p","attribs":{}},{"type":"text","content":"According to IDC (Jan 2025), the proliferation of AI silicon in the data center will experience 24.9% CAGR from 2024 to 2028 in support of capacity demand and infrastructure growth, hence elevating the need for new energy efficiencies. Advanced packaging creativity is bringing the OE directly into the switch silicon package to generate the shortest possible electrical traces resulting in consequential power savings. ASE’s configuration results in shorter electrical path and lower insertion loss, as well as improved power efficiency. The CPO structure is a key interim step in ASE’s progression from pluggable options to optical IO and fully integrated 3D CPO. A major milestone for ASE has been the development of the CPO assembly process flow, which includes substrate warpage and coplanarity control to meet fiber array coupling requirements, and structure and warpage synergy for both edge (horizontal) and surface (vertical) fiber coupling. All these areas are critical to ensuring optimized data throughput while minimizing optical related losses.","length":1058,"tagName":"p"},{"type":"text","content":"As bandwidth demands grow exponentially, the current faceplate-pluggable (FPP) solutions show roadmap limitations in density, power, and cost. The increasing switch speeds also lead to an increase in SerDes interconnect power as a percentage of the total switch power. This is driving the need to move the optics from the FPP into the enclosure closer to the switch ASIC. On-board optics have been adopted as a first step...