TOPPAN : Transcript of Electronics Business Strategy Briefing

Electronics Business Strategy Briefing December 10, 2025

[Company Name] TOPPAN Holdings Inc.

[Event Type] Analyst Meeting

[Event Name] Electronics Business Strategy Briefing

[Date] December 10, 2025

Satoshi Oya Representative Director, Senior Managing Executive Officer & COO, TOPPAN Holdings Inc.

Tetsuro Ueki Senior Managing Executive Officer, Electronics Division, TOPPAN Inc.

Kazunori Katsumura Executive Officer, Deputy Head of

Electronics Division, TOPPAN Inc.

Akihiko Furuya Executive Officer, Semiconductor Subdivision, Electronics Division, TOPPAN Inc.

Masahiro Tada Executive Officer, Display Subdivision, Overseeing Business Strategy Department, Electronics Division, and General Manager of R&D Strategy Office, TOPPAN Inc.

Moderator: Hello, everyone. Thank you very much for taking the time out of your busy schedules to join the Electronics Business Strategy Briefing of TOPPAN Holdings Inc.

Present today are Tetsuro Ueki, Senior Managing Executive Officer and head of the Electronics Division of Toppan Inc.; Kazunori Katsumura, Executive Officer and deputy head of the Electronics Division; Akihiko Furuya, Executive Officer and head of the Semiconductor Subdivision, Electronics Division; Masahiro Tada, Executive Officer and head of the Display Subdivision, Electronics Division; and Satoshi Oya, Representative Director, Senior Managing Executive Officer & COO of TOPPAN Holdings Inc.

Today, Mr. Ueki, Mr. Katsumura, and Mr. Furuya will walk you through the business strategy for the semiconductor-related business, which is the growth area within the Electronics segment, following the presentation materials. After their explanation, we will move on to the Q&A session. The entire meeting is scheduled to run for up to 90 minutes.

The presentation materials are available on the TOPPAN Holdings website's Investors section under Materials for Results Briefings. We encourage you to review them.

Before we begin, please note that today's presentation may include forward-looking statements based on current assumptions and projections. These statements are subject to risks and uncertainties, and actual results may differ materially from these forecasts. Thank you for your understanding.

With that, I would now like to turn the floor over to Mr. Ueki, who will begin with an overview of the Electronics business.

Ueki: I would now like to explain the business strategy for the Electronics segment. I am Ueki, head of the Electronics Division. Today, we plan to walk you through the content in five parts, as shown here.

First, I will speak about the overall picture of the Electronics segment and the general direction of the business. Next, I will outline the semiconductor packaging business, which is our growth driver, and explain our business strategy, including the key areas we intend to target. We will then move on to the market trends within those focus areas. Fourth, we will discuss our technology road map for those areas and the background behind it. And lastly, we will introduce the specific initiatives we are undertaking to realize that technology road map.

To begin, let me provide an overview of the Electronics segment.

In FY2024, the Electronics segment recorded net sales of JPY283.3 billion, non-GAAP operating profit of JPY53.4 billion, and a non-GAAP operating margin of 18.9%. The Electronics segment accounted for 16% of TOPPAN Holdings' consolidated net sales. Within this, the semiconductor-related businesses, centered on the semiconductor packaging business, generated sales of JPY194.8 billion; while the display-related businesses, primarily anti-reflective films, light control films, and small- and medium-sized TFTs, generated sales of JPY88.5 billion.

Next, I will cover the Electronics business plan for FY2025.

As for the photomask business, Tekscend Photomask has become an equity-method associate, and starting in FY2025, it will no longer be included in our reported sales and operating profit. Other items are the same as those presented at the earnings briefing, so I will forgo the detailed explanation here.

Next, let me explain the strategic direction of the Electronics segment using this slide.

Within the semiconductor business, the semiconductor packaging business, which we will discuss in detail today, is positioned as a priority business. For FC-BGAs, we will focus on the high-end market, especially AI-related applications. At the same time, we will promote the development and launch of advanced semiconductor packaging such as glass-core substrates and organic RDL interposers. In the display business, we will begin operating a new ultra-wide production line for anti-reflective films in 2026. For the quantum dot business, we will establish a nanomaterials business centered on materials, and for light control films, we will expand new product lines for automotive applications. In addition to these efforts to expand the business, we will also advance structural reforms in low-profit businesses.

Through these initiatives, the overall direction of the Electronics segment is to concentrate management resources on the high-value-added semiconductor packaging business and to implement a portfolio shift toward businesses where our proprietary technologies can be fully leveraged, thereby accelerating business expansion.

Next, I will discuss the medium- to long-term outlook for the Electronics segment.

We position the semiconductor business as our growth driver, and by supplying leading-edge key devices that leverage our technological strengths, we aim to maintain high profitability. As shown in the slide, for the semiconductor business, we aim for a sales CAGR of 26% and a non-GAAP operating margin of 30%, driven by the expansion of AI applications for FC-BGAs and the launch of advanced semiconductor packaging businesses.

For the Electronics segment as a whole, we aim to achieve a sales CAGR of 22% and expand sales to JPY350 billion by fiscal 2030.

From here, I will go into detail about the semiconductor packaging business, which is one of our priority businesses. First, I will explain the business overview and strategy.

Let me once again explain what an FC-BGA, the core product of our business, is. An FC-BGA is a high-density semiconductor package substrate that enables the high-speed and multifunctional operation of LSI chips used in network equipment, server CPUs, generative AI, consumer electronics, and automotive devices.

If the IC chip is considered the brain, then the FC-BGA corresponds to the nervous system, playing the role of instantly transmitting vast amounts of information and energy. We have independently advanced microfabrication technologies and built-up circuit formation technologies to develop high-density wiring substrates, and we continue to supply products that meet the miniaturization requirements of semiconductor processes.

Next, I will explain the current business domains within our FC-BGA business.

The pie chart on the left shows the general breakdown of FC-BGA market applications in 2024. High-end applications such as high-end switches and servers account for 25% of the overall market, while consumer and automotive applications make up the remaining 75%.

By contrast, the pie chart on the right shows our product mix. As you can see, the ratio of high-end applications is 83%, far exceeding the market average. We will operate our business with a focus on high-value-added markets such as high-end switches and servers.

This slide shows our position in FC-BGA substrates for high-end switch applications.

High-end switches aggregate all communication across the network and process it at high speed with stability. In this field, through our strong technological capabilities and stable supply, we have built a position as the number three player globally in FY2024.

From here, I will explain our focus areas within the semiconductor packaging business, including FC-BGAs, as part of our strategy going forward.

As summarized in the table on the left, we have defined three areas, high-end switches, AI accelerators, and server CPUs, as focus areas for the next phase. For AI accelerators, as shown in the upper portion of the triangular diagram on the right, we are specifically targeting AI ASICs, a domain where customization is valued more than sheer scale. Our approach is to make technological superiority our source of competitiveness and to focus on high-end areas where we can fully leverage that strength.

In line with this, the business domains we previously described using terms such as "for communications servers", "AI, and non-AI", will now be explained based on the definitions shown in this diagram.

The figure on the right illustrates, in schematic form, the structure of large-scale networks in data centers. The lower left of the diagram represents networks consisting of conventional general-purpose servers centered on CPUs, while the right side illustrates networks consisting of AI servers using GPUs and AI ASICs, which have been expanding in recent years.

As shown in the upper part of the diagram, in these data centers, the switches that form the network are defined as general-purpose switches. Meanwhile, the systems that interconnect many AI servers on the lower right, enhancing the processing performance demanded by AI, are defined as AI switches.

Within these AI servers, the blue boxes represent AI ASICs, which are especially strong in inference applications. CPUs, shown in green, are used in both general-purpose and AI servers. Within this landscape, we intend to target areas based on the ARM architecture, which offers particularly high power efficiency.

Next, I will discuss the market outlook for these focus areas.

As shown by the blue segments in the FC-BGA substrate market graph on the left, the three areas we target, high-end switches, AI ASICs, and server CPUs, are expected to drive the expansion of the overall market through strong growth. Against the backdrop of accelerating AI development, we will focus on these high-profit, high-end domains that are expected to expand, and we will continue to grow our business in these areas.

Finally, I would like to explain, as a point of evolution from our traditional business centered on FC-BGAs, how we intend to propose solutions with a view toward addressing broader social issues.

In the focus areas we are targeting, not only is further advancement required for conventional FC-BGAs, as shown in the center of the slide, but evolution aligned with new trends such as photonics-electronics convergence is also necessary. In addition, support for glass cores as a material and new package formats such as interposers will be key technologies in this domain.

To address these challenges, we will integrate our expertise in FC-BGA fine-line wiring and multilayering technologies, our glass-handling capabilities developed through the display business, the LSI design and process-cleaning expertise accumulated through the semiconductor business, and CMP slurry technologies held by our group company TOPPAN Infomedia. At the same time, by collaborating with customers, partner companies, and universities, we will continue to grasp emerging needs and promote technology development.

In parallel, to expand our business scale, we will bring new production lines online in Japan and overseas in line with customer needs, thereby strengthening our manufacturing structure. By taking this approach, developing solutions that address social issues emerging alongside the acceleration of AI and viewing semiconductor packaging as a whole, we will advance our transformation from an FC-BGA business into a semiconductor packaging solutions business.

Katsumura: I am Katsumura, deputy head of the Electronics Division. From here, I will explain the market trends that form the backdrop to the focus area strategies that Mr. Ueki has just described.

This chart shows the share of AI semiconductors within global semiconductor demand.

The AI semiconductor market is expected to grow approximately sevenfold from 2022 to 2030, driving the expansion of the overall market. Cloud demand, primarily for servers related to our focus areas, is likewise expected to grow along with this trend.

In addition, the rise of AI will lead to an explosive increase in data traffic.

We are entering an era in which everything in the world generates data, and global data volume is projected to expand one hundredfold over the 20 years from 2020 to 2040.

To process this massive amount of data, the structure of data centers themselves is undergoing change.

In AI model development, the computational volume required has become so great that it can no longer be contained within the GPU installed in a single AI server. To process this efficiently, multiple GPU servers are connected in parallel, and the data center as a whole is treated as one enormous computer. Moreover, AI processing constantly synchronizes operations across multiple servers while performing computations across server boundaries. As a result, communication with elements outside server enclosures via the network switch becomes far more frequent than in conventional networks, and this communication performance is also critical to the performance of AI.

Consequently, while networks are shifting toward architectures that achieve both "scale-up", boosting the performance of each AI server; and "scale-out", interconnecting many servers in parallel for distributed processing, the performance required of network switches is also becoming increasingly advanced.

As a result, in one of our focus areas, the data-center switch market, we expect shipments of switches for AI servers to increase 3.2-fold over the six years from 2024 to 2030, and we also expect unit prices and total shipment value to show a steady upward trend. In this way, AI-server switches are becoming the growth driver, and we believe the overall network-switch market will continue to expand.

Next, I will explain the demand outlook for AI ASICs, which is another focus area.

In order to utilize AI, there are two phases: the learning phase, in which foundational models are developed; and the inference phase, in which trained models are used. The performance required of AI servers differs in each phase. In the learning phase, enormous computational power is needed to repeatedly feed back results and improve the model. In the inference phase, the requirement is to generate outputs quickly using an already trained model. As trained foundational models accumulate, we expect demand to gradually shift toward inference applications as we approach 2030.

As these required AI use cases evolve, the needs for AI semiconductors that enable them also change.

On the left side of the diagram, CPUs/GPUs perform computation step by step through software control, exchanging data between memories. This gives them high general-purpose flexibility, but they are not optimized for specific tasks.

By contrast, the custom circuitry on the right, namely ASICs, is designed from the outset to be optimized for specific processing, such as inference. This makes it possible to minimize software control and accelerate processing while also optimizing and shortening wiring, which significantly reduces power consumption.

From the perspective of both speed and efficiency, market needs are increasingly shifting toward using high-performance GPUs for learning workloads that require massive computation and AI ASICs for inference workloads.

As a result, the scale of shipments for AI ASICs, whose power-efficiency advantages are even more important for inference, is expected to grow at a high annual rate of 16% between 2024 and 2030.

In addition, the high degree of customization required in AI ASIC development is one of the reasons we have defined this as a focus area.

Lastly, let me explain the trend for server CPUs, one of our focus areas.

CPUs based on x86 architectures, adopted by companies such as Intel, AMD, and IBM, long held an overwhelming share. In recent years, particularly in AI servers where power consumption is high, the share of CPUs based on ARM architectures, which offer superior power efficiency, has been increasing.

Thus, the three focus areas we are targeting, high-end switches, AI ASICs, and server CPUs, are all areas defined by looking squarely at the social issues emerging from the growing needs of AI.

Furuya: I am Furuya, head of the Semiconductor Subdivision. Up to this point, we have explained how our focus areas are expanding in line with AI-driven demand. From here, I will explain our technology road map designed to address these changes, as well as the technical background behind it.

This slide shows the road map illustrating how our semiconductor packaging technologies will evolve.

First, regarding the conventional FC-BGA substrates shown in the lower portion of the road map, we will continue to enhance their technological value not only by supporting large-size, high-layer-count structures, but also by enabling optical connections between boards for the IOWN 2.0 generation and, further, by enabling optical connections between chips. In parallel, we are promoting the launch of new production lines at our Niigata plant and preparing to begin mass production at our Singapore plant.

In the upper portion of the road map, the area of advanced semiconductor packaging, we will create high-value-added products by advancing technology development of chiplet structures that combine FC-BGAs with silicon interposers, as well as glass cores, glass interposers, and organic RDL interposers. Development will proceed at the Advanced Semiconductor Packaging Development Center, and at this stage, our plan is to carry out mass production at the Ishikawa plant. Through these efforts, we aim to contribute to meeting the social challenges of rapidly increasing data transmission requirements and the demand for lower power consumption in network switches and AI applications by supplying semiconductor packages built with new technologies.

From here, I will explain the background to our technology road map, especially the performance requirements for semiconductor packages in 2030 and the challenges associated with them.

To begin, let me discuss the expected transmission performance of next-generation AI networks. Although generative AI has already become familiar in today's world, next-generation use cases such as autonomous driving and remote medicine will require real-time capability together with extremely high information density. According to our estimates, data-center transmission speeds in 2030 will need to reach 800 Tbps, 32 times the level of 2020, offering extremely high speed and low latency.

Next, I would like to introduce the technology trends that will be necessary to achieve this 800 Tbps transmission capability.

The first is wiring miniaturization. As AI semiconductors become more advanced, wiring miniaturization becomes critically important in order to realize heterogeneous chip integration and chiplet structures. On the performance side, in order to complement Moore's Law in the face of shrinking I/O pitch on semiconductor chips, it is necessary to maximize interconnect density and secure high bandwidth.

On the power-efficiency side, minimizing parasitic capacitance and reducing inter-die resistance and capacitance characteristics are required. At the same time, shrinking the physical size of the system also contributes to overall miniaturization and reduced form factor. In this way, from the perspectives of performance, power, and area, wiring miniaturization is expected to deliver substantial value, and by 2030 line width and spacing will be required to fall below 1 micron.

The next challenge is the structural configuration of semiconductor packages required for 2030.

Traditionally, as shown on the left, it was common to integrate all necessary functions into a single chip. However, the pursuit of higher performance through chip miniaturization and scaling has run into the limitations of semiconductor manufacturing complexity and cost.

The breakthrough for this challenge is the chiplet structure shown on the right. This technology divides functions into separate chips that are manufactured individually, such as logic chips and memory, and then reassembles them at high density on top of a large interposer and a large FC-BGA substrate. As you can see, large-scale integration and the heterogeneous combination of optical devices, capabilities that could not be achieved with a single monolithic chip, require the support of larger package components such as interposers and FC-BGA substrates. Specifically, the size of FC-BGA substrates is expected to exceed 200 millimeters by 2030.

However, although silicon interposers, which are currently mainstream, excel in fine-pitch capability, their circular shape means that yield decreases as size increases. As a result, from an economic efficiency standpoint, silicon interposers are approaching their limits in terms of scalability. For this reason, next-generation interposer technologies are expected, technologies that can support large panel formats and still achieve miniaturization performance rivaling silicon interposers.

Another major challenge is photonics-electronics convergence.

As noted earlier, achieving the required 800 Tbps transmission speed in 2030 using conventional electrical signaling over conventional distances would lead to transmission loss far beyond acceptable limits, making such systems infeasible. One proposed solution to meet the required transmission-loss levels is the use of optical transmission.

Please look at the future-system diagram on the right. By placing optoelectronic conversion devices immediately adjacent to the semiconductor chip, the distance over which electrical transmission occurs is shortened. At the same time, communication between chips would use low-loss optical transmission via fiber ribbons and optical waveguides. This type of architecture must be developed in order to minimize transmission loss.

Thus far, I have described the major technology trends required in advanced semiconductor packaging, miniaturization, new interposers, and photonics-electronics convergence.

From here, I will explain the specific initiatives through which we intend to deliver solutions that address these evolving market requirements.

To improve semiconductor packaging performance in an era defined by AI advancement, both interposers and FC-BGA substrates must evolve in line with the specifications shown in the center of the slide. For interposers, the requirements include support for large sizes capable of mounting chiplets, high flatness, high-speed and high-capacity transmission, and low power consumption. To address these needs, we are promoting the development of design and manufacturing technologies for glass interposers, as well as large-format submicron organic RDL interposers fabricated using a damascene process in a panel format.

For FC-BGA substrates, the requirements include miniaturization and embedded components, which we will address through further advances in the FC-BGA manufacturing technologies we have built up over time. For high flatness, high rigidity, low thermal expansion, and low transmission loss, we will develop new core materials, specifically glass cores. For high-speed transmission, we will focus on supporting optical transmission.

Today, among these initiatives, we will explain in detail three key technologies essential to realizing our strategy: submicron organic RDL interposers, glass cores, and optical-transmission solutions.