Agilent Technologies, Inc. · NYSE:A

Agilent Technologies — Intel Developer Forum (IDF) 2003

20 slides from Agilent Technologies's conference presentation, September 2003

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  2. Slide 2: Agenda

    AGENDA Agilent Enables Engineers to Work the Wave of PCI Express Technology • Agilent and the PCI Express Technology Wave • Live Demonstrations at IDF • Agilent New Product Announcements at IDF • Agilent - The PCI Express Portfolio of Choice Agilent

  3. Slide 3: PCI Express - Industry Benefits and Design Challenges

    PCI Express - Industry Benefits and Design Challenges Benefits • Addresses demand for higher performance – more bandwidth • Reduce infrastructure costs • Solves physical limitations of parallel buses • Brings fragmented standards under single umbrella Challenges • Signal integrity is mission critica

  4. Slide 4: Agilent – The Industry Leader in PCI Express Design, Test & Mgt Tools

    Agilent – The Industry Leader in PCI Express Design, Test & Mgt Tools • Agilent test tools meet PCI Express challenges – Physical layer test Coverage – Protocol layer test Dramatically increased test coverage Agilent Validation Error insertion Increased Probing challenges solved Confidence – System

  5. Slide 5: Agilent – The Industry Leader in PCI Express Design, Test & Mgt Tools

    Agilent – The Industry Leader in PCI Express Design,Test & Mgt Tools SDRAM FLASH ADC FPGA RMP 3.0 SDRAM USB 2.0 SDRAM FLASH RMP 3.0 Remote Mgmt & ADC FPGA SDRAM USB 2.0 Diagnostics RMC Today’ s Focus KVM Protocol Validation E2960 PCI Express Protocol Exerciser/Analyzer Test Card Mid-bus Probe System

  6. Slide 6: Agenda

    AGENDA Agilent Enables Engineers to Work the Wave of PCI Express Technology • Agilent and the PCI Express Technology Wave • Live Demonstrations at IDF • Agilent New Product Announcements at IDF • Agilent - The PCI Express Portfolio of Choice Agilent

  7. Slide 7: Live PCI Express Demonstrations at IDF

    Live PCI Express Demonstrations at IDF Protocol Test Protocol Protocol Remote Card Exerciser Analyzer Managment and KVM Config / OS SDRAM FLASH Softwar / ADC FPGA SDRAM RMP 3.0 USB 2.0 Transactio/ Protocol Layers Jointly developed with Intel System test for Logic Analyzer Protocol/ Transaction/ + Da

  8. Slide 8: Serial Protocol Tester XC

    Serial Protocol Tester XC Universal Hardware 8 x 3.125 GB/s Duplex Module Bandwidth x1 x1, x4 x1, x4, x8 Personalities Application Analyzer Analyzer Applications Patented dynamic Exerciser Personalities trigger conditions Exerciser investigations Protocol Protocols Personalities PCI Express Investig

  9. Slide 9: Simulation and Test

    Simulation and Test Agilent Technologies and Denali Software join PureSpec Verification Tool in development of comprehensive validation process to speed chip designs • Speed development by coordinating pre- silicon verification tests with post-silicon test and analysis efforts • Common packet viewin

  10. Slide 10: Agilent Protocol Test Card for PCI Express Compliance Testing

    Agilent Protocol Test Card for PCI Express Compliance Testing Collaboration and joint development with Intel: • Cost-effective compliance solution • Easy-to-use - GUI/push-button solution - Pre-programmed tests No programming effort - Pass/Failed report • Improves design quality, compliance and acce

  11. Slide 11: PTC An Integral Part of Intel Enabling Programs

    PTC An Integral Part of Intel Enabling Programs • Co-developed PTC - important testing tool for use with Intel PDKs • Already in use in Intel Interoperability Lab • Multi-speed support ensures entire industry can benefit from use: - Clients - Servers - Communications • Aids in delivery of compliant

  12. Slide 12: System Level Validation Ideal for Prototype Turn-on

    System Level Validation Ideal for Prototype Turn-on • Trace System Problems to Root Cause – Time correlated multi-bus / multi-node measurements • Full Packet Analysis and Decode – Industry leader in packet identification • Complete header information • Initial data bytes • Sequential packets • Valid

  13. Slide 13: Physical Layer Test

    Physical Layer Test Stimulus/Response with Pulse Generator / Oscilloscope Combination • Stress tests for resolution of critical signal integrity issues • Stimulus - programmable 3.35GHz pulse and pattern generator Full control on signal quality makes stress-test easy and repeatable Generates real-li

  14. Slide 14: Agenda

    AGENDA Agilent Enables Engineers to Work the Wave of PCI Express Technology • Agilent and the PCI Express Technology Wave • Live Demonstrations at IDF • Agilent New Product Announcements at IDF • Agilent - The PCI Express Portfolio of Choice Agilent

  15. Slide 15: 1/2 Mid-bus Connectorless Probing

    1/2 Mid-bus Connectorless Probing • 50% reduction in board space • Soft Touch Technology • No slot connector required • Reduced electrical load • Eases routing of board traces • Ease of use - just hand tighten • Most reliable probing - Passive probing runs cool - Adjusts to uneven board surfaces N42

  16. Slide 16: Protocol Analyzer Mid-bus Probe

    Protocol Analyzer Mid-bus Probe • Soft Touch technology Protocol • Only vendor offering mid-bus probes Analyzer for logic analyzer and protocol analyzers • Extend measurement application of the protocol analyzer respectively Amplifier increases the test coverage • Flexible connectivity of interposer

  17. Slide 17: Remote System Operation

    Remote System Operation Benefits: SDRAM FLASH ADC FPGA RMP 3.0 • Minimized space requirement SDRAM USB 2.0 • Utilizes available system interfaces • Turn-key solution including software • Flexibility to change look-and-feel of WEB based GUI • Rich feature set providing redirection of keyboard, video,

  18. Slide 18: Agenda

    AGENDA Agilent Enables Engineers to Work the Wave of PCI Express Technology • Agilent and the PCI Express Technology Wave • Live Demonstrations at IDF • Agilent New Product Announcements at IDF • Agilent - The PCI Express Portfolio of Choice Agilent

  19. Slide 19: Agilent PCI Express Test Solutions

    Agilent PCI Express Test Solutions Remote Managment • Broadest selection of design and test SDRAM FLASH ADC FPGA RMP 3.0 SDRAM USB 2.0 and KVM equipment optimized for PCI Express Protocol Exerciser across the layers and beyond. Protocol Analyzer Config/OS Software/ • Complete PCI Express system Tran

  20. Slide 20: Agilent Booths

    Agilent Booths: Intel Pavilion - # 219 General Floor - # 441

Agilent Technologies — Intel Developer Forum (IDF) 2003 on 6ix