Micron Technology, Inc. · NASDAQ:MU
Micron Technology — Flash Memory Summit 2008
23 slides from Micron Technology's conference presentation, August 2008
Slide 1: Optimizing NAND Flash Performance
Optimizing NAND Flash Performance Ryan Fisher (rfisher@micron.com) Sr. Applications Engineer Micron Technology, Inc. Santa Clara, CA USA August 2008 1
Slide 2: NAND Usage by Application
NAND Usage by Application NAND Flash is finding its way into increasingly diverse end systems and applications—all with different requirements when it comes to NAND Flash • Total density – Single package vs. multiple packages – Package type (TSOP/BGA/LGA) • Configuration of NAND within a system – Si
Slide 3: NAND Usage by Application
NAND Usage by Application (Millions of MB) 60,000,000 AIMM GPS 50,000,000 Gaming TV Portable Media Players 40,000,000 Camcorder/Digital Camera Other Wireless Devices Cell Phones 30,000,000 Solid-State Drives Disk Drives 20,000,000 Smart Cards USB Flash Drives Flash Cards 10,000,000 Printers Personal
Slide 4: NAND Array Performance
NAND Array Performance NAND array performance times (tPROG, tR, tBERS) have a major influence on NAND throughput performance • They’re outside the control of the host system • They vary for SLC and MLC NAND devices – Even varies from SLC to SLC device and MLC to MLC device To proactively improve ove
Slide 5: Improving NAND Performance
Improving NAND Performance Various methods can be used to improve NAND Flash performance • Optimize NAND AC timings – Using minimum timings available for a given NAND device • Optimize NAND bus activity – Avoid long idle times on the NAND bus during operations • Cache Operations – Read and program c
Slide 6: AC Timing Optimization
AC Timing Optimization Optimizing NAND AC timings (specifically tWC/tRC) can have a dramatic impact on performance • It can be a less costly/complex method of improving NAND Flash performance in non-optimized systems (i.e., updating a count/timing register in a host controller) • It can have a signi
Slide 7: AC Timing Optimization
AC Timing Optimization Example effects of optimized vs. non-optimized AC timings Five mass storage class devices with different NAND controllers were t analyzed to determine what WC timings were being utilized given a t NAND data sheet specification of 20ns WC MIN: Time % increase Time to input Cont
Slide 8: NAND Bus Activity Optimization
NAND Bus Activity Optimization Optimizing NAND bus activity to avoid excessive idle time represents another system-level interaction with the NAND device that is sometimes overlooked when trying to improve overall NAND Flash performance Common reasons for NAND bus idle time 1. System limitations dea
Slide 9: NAND Bus Activity Optimization
NAND Bus Activity Optimization Example of two-plane page program operation issued to a NAND Flash device in customer application • Total extra time added for inputting of data due to “idle” times shown above is ~166µs • This equates to a 95% time increase compared to the time required for a optimize
Slide 10: Cache and Multi-Plane Operations
Cache and Multi-Plane Operations Cache and multi-plane operations represent another means of improving NAND Flash device performance • Cache operations – Require slightly different NAND Flash commands than normal PROGRAM/READ operations • Multi-plane operations – Require different NAND command codes
Slide 11: 4KB Page MLC Programming Comparison
4KB Page MLC Programming Comparison = Command, Address, ~ 4.4 MB/s and Data Inputs Page Program Assumes 20ns tWC tProg tProg tProg Command, Address, Command, Address, Command, Address, and Data for and Data for and Data for Page 0 Page 1 Page 2 Command, Address, and Cache Programming ~ 4.8 MB/s Data
Slide 12: 4KB Page MLC Programming Comparison
4KB Page MLC Programming Comparison = Command, Address, Page Program And Data Inputs tPROG tPROG ~ 4.4 MB/s Assumes 20ns tWC Command, Address, Command, Address, Command, Address and Data for and Data for and Data for Page 0 Page 1 Page 2 Command, Address, and Data for Page 0 Plane 1 Two-Plane Page P
Slide 13: 4KB Page MLC Read Comparison
4KB Page MLC Read Comparison = Read Time = Data output = Command and Address ~27.3 MB/s Page Read Assumes 25ns tRC tR tR Data Output Data Output Command and Command and Read output from Page 0 Read output Address for Read of Address for Read from Page 1 Page 0 of Page 1 ~36.5 MB/s Cache Read Assumes
Slide 14: 4KB Page MLC Two-Plane Read Comparison
4KB Page MLC Two-Plane Read Comparison = Array Read Time = Data Output = Command and Address ~ 27.3 MB/s Page Read Assumes 25ns tRC tR tR Data Output Data Output Command and Command and Read output Read output from Page 0 Address for Read of Address for Read from Page 1 Page 0 of Page 1 ~ 32.4 MB/s
Slide 15: 4KB Page MLC Erase Comparison
4KB Page MLC Erase Comparison = Command and Address Block Erase tBERS ~143 MB/s Command and Address for Block Erase Two-Plane Block Erase ~286 MB/s tBERS Command and Address for 2 Blocks to Erase, Plane 0 and Plane 1 0 1ms 2ms 3ms 4ms 5ms 6ms Santa Clara, CA USA August 2008 15
Slide 16: Interleaved Operations
Interleaved Operations Interleaved operations can be used to improve NAND Flash array performance • Depending on the system configuration, interleaved operations may be easier to implement that multi-plane operations • Interleaved operations have the benefit of requiring: – Little extra support from
Slide 17: Interleaved Operation Two-Plane Page Program
Interleaved Operation Two-Plane Page Program = Command, Address and = Command, Address and = Array Program Time Data Inputs Plane 0 Data Inputs Plane 1 Die 0 on CE# tProg tProg Die 1 tProg tProg on CE# Die 0 tProg tProg on CE2# Die 1 tProg tProg on CE2# 0 400µs 800µs 1200µs 1600µs 2000µs 2400µs Sant
Slide 18: Multi-Channel Operations
Multi-Channel Operations Multi-Channel Operations Offer true operation Two-Channel Configuration Example parallelism for improving Host NAND NAND Flash performance in a system Require increased number of signals from the host system to support this configuration Santa Clara, CA USA August 2008 1
Slide 19: Multi-Channel Operations
Multi-Channel Operations Some packages with Signal Assignments for ONFI-Defined x8 LGA multiple NAND die offer multi-channel commands and I/O setups Two separate sets of command signals • CLE1, ALE1, WE1#, RE1#, WP1#, CE1# • CLE2, ALE2, WE2#, RE2#, WP2#, CE2# Two separate sets of I/O signals • I
Slide 20: Improving NAND Performance
Improving NAND Performance Any of the techniques discussed will improve NAND Flash performance, and combining two or more of these techniques will provide further performance enhancements Some of the more common combinations of these techniques are: • Multi-channel configuration with multi-plane ope
Slide 21: Resources for Improving NAND Flash Performance
Resources for Improving NAND Flash Performance Micron offers additional information for improving NAND Flash performance, available on the NAND Flash Technical Notes web page at: www.micron.com/product/nand/technotes • TN-29-01: NAND Flash Performance Increase – Using the Micron PAGE READ CACHE MODE
Slide 22: Thank You
Thank You ©2008 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any
Slide 23: Biography
Biography Ryan Fisher has a BSEE from the University of Florida and has worked in the semiconductor industry for 7 years Positions held: • Motorola SPS (Austin, TX): Applications Engineer for Wireless Baseband Processors • Micron Technology (Boise, ID): Sr. Applications Engineer for NAND Flash m