Technoprobe Spa · MIL:TPRO
Technoprobe Spa — Investor Presentation (May 2026)
48 slides from Technoprobe Spa's investor presentation, May 2026
Slide 1: Technoprobe S.p.A. Company Presentation
Technoprobe S.p.A. Company Presentation May, 2026
Slide 2: Disclaimer
Disclaimer This document has been prepared by Technoprobe S.p.A. (the “Company”) solely for use in the presentation. This document does not constitute or form part of any offer or invitation to sell, or any solicitation to purchase any security issued by the Company. The information contained and th
Slide 3: Innovation begins with us
Innovation begins with us A leading company in the field of semiconductors and microelectronics INNOVATION BEGINS WITH US
Slide 4: Company Overview
Company Overview Revenue Ebitda Net Income Net Financial Position Mkt Cap 2025 Key financial metrics €628.4m €201.4m €98.8m €684.2m ~€18,5bn +16% 32% 16% as at as at YoY EBITDA margin on revenues 12/31/2025 5/18/2026 Shareholding Structure Leading player in designing and manufacturing of probe cards
Slide 5: Where we are
Where we are Headquartered in Italy with branches in Europe, America, and Asia >3.3k Employees 3 Continents 10 Countries 23 Legal Entities TP TP Japan Germany TP Korea TP America DIS Tech DIS Tech DIS Tech TP China MW Plasma 5 TP Italy DIS Tech TP Taiwan YeeWei Harbor Electronics TP Philippines TP D
Slide 6: Testing in the semiconductor manufacturing process
Testing in the semiconductor manufacturing process INNOVATION BEGINS WITH US 66
Slide 7: Our positioning in the testing space
Our positioning in the testing space FRONT END BACK END Wafer fabrication Wafer Testing Assembly Final Testing & pre-assembly Wafer dicing Level & Packaging Level preparation Wafer Level Socket Singulated Die System Level Testing Advanced Packaging Device Interface Board Probe Card INNOVATION BEGINS
Slide 8: The testing phase
The testing phase Probe Card • A probe card is a precision device with microscopic needles or MEMS tips that make electrical contact with each die’s test pads on the wafer • The probe card interconnect a tester (ATE) with dies on a wafer or diced dies for electrical testing. Tester (ATE) • A tester,
Slide 9: The Probe Card
The Probe Card INNOVATION BEGINS WITH US 9
Slide 10: The Probe Card
The Probe Card INNOVATION BEGINS WITH US 10
Slide 11: The Probe Card
The Probe Card Facts Sheet 1 probe card 100000+ Number of contacts interconnecting tester with device 1000A+ Ampere of currents to supply the device 20µm Pad pitch to ATE space transformation of a factor >10x 100W+ Watts of power to dissipate through the card 200Kg+ Withstand a force of hundred kilo
Slide 12: Reference Market
Reference Market INNOVATION BEGINS WITH US
Slide 13: Overview of the Semiconductor Probe Cards market
Overview of the Semiconductor Probe Cards market By segment ($Mn) CAGR % 2019-2024 CAGR % 2024-2028 1.783 2.443 +6.5% 3.133 +6.2% 100% 90% 80% 70% 1.151 1.638 +7.3% 2.060 +5.9% 60% 50% 40% 30% 20% +4.9% 632 805 1.053 10% 0% Logic Memory 2019 2024 2028 Source: Yole – Semiconductor Test Consumables ma
Slide 14: Our reference market
Our reference market 2024 Logic Probe Card market 2024 MEMS Logic Probe Card $1,6 Bn $937 Mn $194Mm $222Mm $286Mm $937 Mn Cantilever MEMS Vertical Other Market Share: 34% Market Share: 60% Source: Yole – Semiconductor Test Consumables market monitor Q3 2024 (Sept.2024) – rounded figures. INNOVATION
Slide 15: Final Testing market – Advanced PCBs
Final Testing market – Advanced PCBs Advanced PCBs ($Mn) CAGR % 2019-2024 CAGR % 2024-2028 778 1.034 +5.9% 1.214 +3.9% 100% 90% 210 290 +6.7% 351 80% 70% 60% 50% 40% 568 744 +5.6% 863 +3.9% 30% 20% 10% Burn-in Boards Device Interface Boards 0% 2019 2024 2028 Source: Yole Test Interface Board market
Slide 16: Final Testing market – Our reference market
Final Testing market – Our reference market 2024 Advanced PCB for semiconductor 2024 Final Test DIB market $1 Bn $744 Mn * $290Mn $744 Mn Device Interface Boards Burn-in Boards Market Share: 6% Market Share*: 8% Source: Yole Test Interface Board market monitor Q3 2024 (Sept.2024) – rounded figures.
Slide 17: Business Model
Business Model INNOVATION BEGINS WITH US
Slide 18: A successful and vertically integrated business model
A successful and vertically integrated business model INNOVATION BEGINS WITH US 18 18
Slide 19: Supported by an open eco-system partnerships
Supported by an open eco-system partnerships Accelerate growth of Priority suppliers complete Probe Card and of PCB Final Test Interfaces by acquisition of DIS Joint Development Projects Joint Development Projects to deliver superior customer to share knowledge value in SOC and Memory
Slide 20: The Probe Card manufacturing process
The Probe Card manufacturing process INNOVATION BEGINS WITH US 20 20
Slide 21: A wide range of highly innovative technologies inside
A wide range of highly innovative technologies inside INNOVATION BEGINS WITH US 21
Slide 22: Vision & Strategy
Vision & Strategy INNOVATION BEGINS WITH US
Slide 23: Challenges & strategic setting
Challenges & strategic setting Evolution of chip technology → Continuous investments in R&D 1 (more than Moore) Scaling slow down as enabler for chiplets, → M&A as accelerator of 3D architectures and new materials technological development → Strategic partnerships Increase in complexity 2 Design and
Slide 24: Growth drivers & trajectories
Growth drivers & trajectories INNOVATION BEGINS WITH US 24
Slide 25: Advanced Packaging: Yield Motivations
Advanced Packaging: Yield Motivations The Reticle: maximum area printable by lithography machine (~ 26mm x 33mm). You cannot manufacture a chip larger than this “frame”. The Solution: AP bypasses the reticle limit by "stitching" high-yield chiplets together to create a system that functions one ultr
Slide 26: Typical processor architecture
Typical processor architecture WHERE OUR PROBE CARDS PLAYS Wafer probe, single to multi-site Wafer probe, compact or full Die or wafer probe Probe card with wafer array PH Single site, large pin UCIe/PCIe count Logic base die and memory stack Probe card with HBM Wafer or die level, R&D project: LSI
Slide 27: Technoprobe as advanced packaging enabler
Technoprobe as advanced packaging enabler Fine pitch and ultra – large pin count High-speed Necessary to effectively probe HPC Short, ultra short and RF-specific needles and HBM’s and all leading-edge product technology to manage high speed interconnect IO, including SiPho High power and thermal • D
Slide 28: A hungry world of wideband applications
A hungry world of wideband applications Exponential increase in number & Increasing reliance type of connected things Bandwidth-hungry applications on the cloud Analog radio frequency Chiplet probing Silicon photonics Satellite communications and High density and high-speed IO inside Chiplet to chip
Slide 29: Technoprobe silicon photonics testing solution
Technoprobe silicon photonics testing solution Fine pitch probing Technoprobe IP align with advanced packaging roadmap usage of standard wafer prober Radio frequency probes Integration of other IP from specific high-speed performances in same probe card segment suppliers solutions flexibility and co
Slide 30: Eclipse photonics
Eclipse photonics Where it applies How it works What it delivers Wafer Reconstituted Optical An autonomous instrument level wafer level Engine • EclipsePhotonics embeds the electronics to Ultra-short autonomously operate when on the tester Vertical • It integrate a programmable unit to execute the M
Slide 31: Probe requirements
Probe requirements PIC S1 S2 EIC S1 Legenda S3 S4 O=Optical DC= DC test only AC= full perf. test including functional ATE= test using ATE ASIC S1 SLT= mission mode test Note: AC may include RF test PIC: photonics integrated circuits EIC: electronics integrated circuits Other chiplet ASIC: Applicatio
Slide 32: HBM Architecture
HBM Architecture Cartoon credit: Applied Material web site FRONT END Enter the High Bandwidth Memory (HBM) segment INNOVATION BEGINS WITH US 32
Slide 33: HBM Test Flow
HBM Test Flow FRONT END Enter the High Bandwidth Memory (HBM) segment INNOVATION BEGINS WITH US 33
Slide 34: HBM: new testing solution
HBM: new testing solution FRONT END Enter the High Bandwidth Memory (HBM) segment INNOVATION BEGINS WITH US 34
Slide 35: HBM Test Flow: microcantilever technology
HBM Test Flow: microcantilever technology Microcantilever needles cannot be arranged to contact bump in a full grid arrangement Needle tip to contact device 3 1 2 Sacrificial pads are necessary to microcantilever end point which shall be enable usage of microcantilever soldered to a PCB/MLC FRONT EN
Slide 36: HBM Test Flow: vertical mems vs. microcantilever
HBM Test Flow: vertical mems vs. microcantilever PCB MLO Vertical MEMS needles can be arranged to contact bump in a full grid arrangement FRONT END Enter the High Bandwidth Memory (HBM) segment INNOVATION BEGINS WITH US 36
Slide 37: FusionLink
FusionLink FusionLink is an advanced interface architecture that combines the best manufacturing technologies & processes to redefine what’s possible for test strategy Main motherboard Best technology: printed circuit board • FusionLink unifies the know-how across The Best Performance (PCB) probe ca
Slide 38: Financial Outlook
Financial Outlook INNOVATION BEGINS WITH US
Slide 39: Mid-terms scenario
Mid-terms scenario* * As presented during CmD on April 14, 2025 INNOVATION BEGINS WITH US 39
Slide 40: FY 2025 revenues
FY 2025 revenues Revenues at 628.4€m up 15.7% YoY Split by end markets Consistent growth in AI 14% Stabilization of volumes in Consumer market 48% 38% Softness in Automotive and Industrial INNOVATION BEGINS WITH US 40
Slide 41: 2026 market outlook & testing perspective
2026 market outlook & testing perspective Geo-Politic Framework • Wartime scenario in the • Export controls shaping • Supply chain Middle East affect products roadmaps regionalization to offset worldwide economic manufacturing stability concentration risk Market Drivers: Volumes & Test Intensity Vol
Slide 42: 2026 - Agreement in principle to strengthen Chinese market
2026 - Agreement in principle to strengthen Chinese market Operating RATIONALE OF THE AGREEMENT Subsidiary 100% Enhance Technoprobe presence in Mainland China through the (TPEG products development of TPEG technology manufacturing and Strengthen the protection of the Technoprobe Group’s know- co
Slide 43: Q1 2026 market drivers
Q1 2026 market drivers Strong growth in AI Revenues at 187.0 €m Slight growth in Consumer market up 15.6% QoQ up 19.0% YoY Recovery in Automotive and Industrial INNOVATION BEGINS WITH US 43
Slide 44: Q1 2026 results
Q1 2026 results Q1 2026 Q1 2025 YoY% Notes Revenues (€m) 187.0 157.2 +19.0% • Organic growth: strong contribution from AI, slight growth in Consumer and recovery in Automotive and Industrial • FX negative impact of €20m Gross Profit (€m) 91.1 70.8 +28.7% • Increasing manufacturing capacity • Ongoing
Slide 45: Capex to Support Organic Growth
Capex to Support Organic Growth €99m ~ €240m 100% Others 10% • Infrastructure and equipment improvement to 90% increase existing manufacturing capacity Yee Wei 80% 22% 70% DisTech 60% 12% • Expansion of machinery fleet for existing production units (same for Logic and HBM) 50% 40% ~ 80% • Constructi
Slide 46: Cernusco Lombardone (Italy) - plant expansion 26-27
Cernusco Lombardone (Italy) - plant expansion 26-27 +4,000 sqm manufacturing area ready end of Q1 2027 Current footprint Greenfield under construction INNOVATION BEGINS WITH US 46
Slide 47: Q2 2026 Guidance
Q2 2026 Guidance Revenues: €266m (+/-3%) Gross Margin: 55% (+/-200bps) Average Q1 '25 Q2 '25 Q3 '25 Q4 '25 Average Q1 '26 Q2 '26* Q3 '26* Q4 '26* Ebitda Margin: 45% 1,052 1,134 1,168 1,163 1,170 1,180 1,177 1,180 3M 1,052 3M 1,170 6M 1,093 6M 1,175 9M 1,119 9M 1,176 12M 1,130 12M 1,177 (+/-200 bps)
Slide 48: 2027 targets anticipated with new 2026 targets
2027 targets anticipated with new 2026 targets INNOVATION BEGINS WITH US 48