Slide 1: Just the right PIC – How advanced test concepts enable fast PIC wafer-level tests
Just the right PIC – How advanced test concepts enable fast PIC wafer- level tests Tobias Gnausch | Sylwester Latkowski 13-03-2024
Slide 2: Electronic-Photonic Test Roadmap for Integrated Photonics
Electronic-Photonic Test Roadmap for Integrated Photonics Jenoptik Webinar 2024 Sylwester Latkowski
Slide 3: Outline
Outline • Integrated Photonics • Wind of the future and some challenges • Electronic-Photonic test for Integrated Photonic Systems • Needs, challenges, and a crystal ball • Photonic Integration Technology Center • Metrology Program at a glance
Slide 4: Photonics is all around round
Photonics is all around round • Tele-communications • Data–communications • Access to information • Streaming • Gaming • Socializing • Banking • Trading • Security
Slide 5: Even more photonics in the future
Even more photonics in the future • Artificial Intelligence • Quantum applications •Even Autonomous transportation more photonics •inSensors everywhere the future
Slide 6: Integrated Photonics System on a Chip
Integrated Photonics System on a Chip • Complex functionalities integrated • Monolithic technologies • Heterogeneous technologies • No single one that suites all • No real standards
Slide 7: Integrated Photonics can be tiny
Integrated Photonics can be tiny • Optical waveguides are in the micron • Multi-IO systems are essential • Several today -> Hundreds soon • High-density optical IOs • Optical alignment challenging • Probing is challenging • No standard IOs on the PIC side
Slide 8: Photonics meets microelectronics
Photonics meets microelectronics • Electronic-Photonic SoC • Economy of scales • Production at volumes • High throughput test solutions • Automated Test Equipment • Highly parallel testing • Electronic-Photonic Probing • Standardization
Slide 9: Electronic-Photonic Test
IPSR eS Electronic-Photonic Test Driving Photonics Manufacturing
Slide 10: Role and importance of PIC testing
Role and importance of PIC testing • Identify known-good-die (KDG) • Push the performance-yield envelope • Create improved accuracy models for the designers to make next generation product • Testing is often a short-hand for • Validation Ignazio Piacentini, Ficontec @ ECOC 2019: • Verification • Sel
Slide 11: Test processes in PIC production chain
Test processes in PIC production chain JePPIX Roadmap 2018 http://www.jeppix.eu/vision 10
Slide 12: Grand challenge: beauty & the beast
Grand challenge: beauty & the beast • Characterization is a ‘beauty’ • Lots of data and information • Good for low volume, MPW, • Essential a ‘startup-phase’ of a product • Resource demanding • Volume ‘unfriendly’ Makoto Okano (AIST), Sylwester Latkowski(TU/e), IPSR-I 2019 • Test is the ‘beast’ • Ne
Slide 13: Test processes in volume production of Integrated Photonics
Test processes in volume production of Integrated Photonics • Ideally as much as possible at wafer level (WLT) – Electrical + optical – RF: available but is it essential here? • Highly automated – Handling – Probing • Highly paralleled • Multiple electrical and optical IOs (simultaneously) • Multipl
Slide 14: WLT: Hybrid probe-cards
WLT: Hybrid probe-cards 2023: Electrical-optical probe-card • Out of plane coupling e.g. gratings • Large MFD, alignment tolerant, tens of optical IOs • DC + Optical • Integration with AT (+1Y?) 2028: Electrical optical probe-card NG • In-plane, edge coupling • 100+ optical IOs • Small MFD, thither
Slide 15: BIST: Built-In-Self-Test
BIST: Built-In-Self-Test 2025: On-chip diagnostics • Temperature monitoring • Open, short CKT 2030: Self-calibration • Parameter monitoring e.g. temp, power, lambda • Feedback + correction signal • Somewhat increased El Ph integration would help 2040: Re-purpose, Adaptive operation modes • Failure-p
Slide 16: Testing of Photonics in Global Technology Roadmaps
Testing of Photonics in Global Technology Roadmaps • Integrated Photonics Systems Roadmap – International 2020 (IPSR-I) • AIM Photonics Academy and PhotonDelta • Electronic-Photonic Test and other chapters with a strong input from PIXAPP and JePPIX • https://photonicsmanufacturing.org/sites/default/
Slide 17: From technology roadmap to industry standards
From technology roadmap to industry standards • IEEE Standards Association Photonics Committee (2019) • IPSR-I Study Group (SG) to identify standardization potential • IEEE SA Project approval request (PAR) • Output from PIXAPP, JePPIX Pilot Line and OpenPICS published at openEPDA.org serves as the
Slide 18: IPSR-I 2024 Sneak peek: Electronic Photonic Test Chapter
IPSR-I 2024 Sneak peek Electronic Photonic Test Chapter 7 Average expected test time 2024 2030 • (More) Compact 6 6.5 TIME [MINUTES] 5 5.4 • Re-Structured 4 5.1 3.8 New input and data 3 • 2 2.3 • Industry-enriched content 1 2 In your hands soon 0 • Wafer Chiplet Module Survey 2024 early preview * TE
Slide 19: Photonic Integration Technology Center
Photonic Integration Technology Center • Joint Innovation Center on Integrated Photonics • Accelerate the industrial uptake of integrated photonics • Access to state-of-the-art photonic chip fabrication and integration facilities • From application requirements to full system design to chip design a
Slide 20: Metrology Program: Objectives and strategy
Metrology Program Objectives and strategy • Product development cycles reduced by at least 3 months • Development of design-for-test methodologies • Next-generation characterization tools and methods to support new product developments - E-O bandwidth test at +100GHz, reproducible and fast linewidth
Slide 21: PITC Metrology Program launching partners
PITC Metrology Program launching partners
Slide 22: Metrology Program: Technical agenda overview
Metrology Program Technical agenda overview Work packages Program management and business WP1 development WP2 Data Analytics WP3 High throughput testing WP4 Test in small batch to volume scale-up WP5 Modular tools and instrumentation WP6 Next generation test and characterization WP7 Talent developme
Slide 23: Thank you!
Credits and sources: Thank you! www.nature.com raith.com JePPIX TU/e www.intel.com WUR Lionix International gigalight.medium.com Questions? SMART Photonics Saxion s.latkowski@tue.nl Effect Photonics The Internet NanolabNL sylwester.latkowski@pitc.nl
Slide 24: UFO Probe Card: High-Volume test solution for PIC Wafer-Level Test
UFO Probe® Card High-Volume test solution for PIC Wafer-Level Test Jenoptik webinar 2024: “Just the right PIC” | Tobias Gnausch
Slide 25: Photonics at Jenoptik
Photonics at Jenoptik
Slide 26: Jenoptik at a glance
Jenoptik at a glance A leading globally operating photonics group Key facts 1991 Year of foundation Villingen- Berlin, DE Dresden, DE >80 Represented in countries Schwenningen, DE Semiconductor, Micro-optics, Metrology medtech opto-electronics >4,400 Employees worldwide Monheim, DE Triptis, DE Bayeu
Slide 27: Organizational structure of the Jenoptik Group
Organizational structure of the Jenoptik Group: Two photonics-based divisions and automotive business Advanced Photonic Solutions Smart Mobility Non-Photonic Division Solutions Division Portfolio Companies Semiconductor & Life Science & Others Electronics Smart Mobility Medical Technology Optics, mi
Slide 28: UFO Probe Card
UFO Probe® Card High-Volume test solution for PIC Wafer-Level Test
Slide 29: UFO Probe Card Enables High-volume Wafer Level Tests of PICs
UFO Probe® Card Enables High-volume Wafer Level Tests of Photonic Integrated Circuits (PICs) JENOPTIK’s High-Volume test solution for PIC Wafer-Level Test ▪ Focus: High-Volume Manufacturing Eco-system Courtesy of Sicoya ▪ Simultaneous optical and electrical probing enables utilization of existing IC
Slide 30: UFO Probe Card Enables High-volume Wafer Level Tests
UFO Probe® Card Enables High-volume Wafer Level Tests of Photonic Integrated Circuits (PICs) Probe card key figures ▪ Standard prober interfaces Monolithic optical module ▪ Monolithic optical module with up to 32 channel ▪ Alignment insensitive optical coupling for vertical emitting PICs ▪ Simultane
Slide 31: UFO Probe Card Working Principle
UFO Probe® Card Working Principle Alignment insensitive test solution for PIC Wafer-Level Test Optical concept compensates prober alignment tolerances. Expected input light intensity profile of Grating Coupler Shaped intensity output profile of Prober position tolerance probe card Optical probe Opto
Slide 32: Probe card types: UFO Probe Cantilever
UFO Probe® Card Probe card types UFO Probe® Cantilever Cantilever Time saving simultaneous optical and electrical probing ▪ Works for vertical emitting PICs ▪ Monolithic optical module with up to 32 optical channels ▪ Optical standard pitch of 127µm and 250µm or individual pitch ▪ Cantilever needle
Slide 33: Probe card types: UFO Probe Vertical
UFO Probe® Card Probe card types UFO Probe® Vertical Vertical High pin count and fine pitch probing ▪ For small pad sizes down to 35µm (square). ▪ Small needle pitch: ≥ 40µm ▪ High needle count: up to 30000 or more, ▪ Pointed or flat needle tip (pad and bump probing) ▪ Optical Channels: up to 32 or
Slide 34: UFO Probe Card Further developments
UFO Probe® Card Further developments UFO Probe® ATE Tester operability Ongoing joint efforts with Advantest for ▪ Integration for direct docking ATE systems streamlined ATE integration ▪ UFO Probe Technology for vertical emitting PIC test ▪ Path to high count optical I/O and multi-site Optical conne
Slide 35: UFO Probe Card Overview
UFO Probe® Card Overview Specifications Current generation Future generations Component to be tested Electronic and photonic integrated circuits (EPIC); EPICs for transceivers, photodiodes, (Device under test/DUT) optical transceivers for data transmission and biosensors and Solid State LIDAR teleco
Slide 36: UFO Probe Card Jenoptik Competencies
UFO Probe® Card Jenoptik Competencies ▪ Design: Optical module and general E/O-probe card Innovation ▪ Manufacturing and supply chain ▪ Micro-assembly and alignment of optical and electrical modules ▪ Optical test and verification in lab: customized test rig ▪ Test under manufacturing conditions: UF
Slide 37: UFO Probe Card Jenoptik Competencies
UFO Probe® Card Jenoptik Competencies ▪ Design: Optical module and general E/O-probe card Innovation ▪ Manufacturing and supply chain ▪ Micro-assembly and alignment of optical and electrical modules ▪ Optical test and verification in lab: customized test rig ▪ Test under manufacturing conditions: UF
Slide 38: Supporting the digital world.
Supporting the digital world.