Synopsys, Inc. · NASDAQ:SNPS
Synopsys — Technical Presentation (2002)
13 slides from Synopsys's technical presentation, 2002
Slide 1: Software Development and Test on Virtual ECU
Your Name (and company logo if desired — change this on slide master) Software Development and Test on Virtual ECU Manfred Thanner, Motorola Michael Rohleder, Motorola Michael Seibt, Synopsys SNUG Saber 2002 1
Slide 2: Overview
2 Overview • Full Chip Simulation Technology • HCS12 - Saber Co-Simulation • Example Application • Summary • Outlook SNUG Saber 2002 2
Slide 3: What is a Full Chip Simulator?
3 What is a Full Chip Simulator ? A virtual prototype of a microprocessor with its blocks: – Core Model – Memory Models (RAM, Flash ) – Internal Bus Bridges – Network Communication Peripherals (FlexCAN, SPI, SCI, etc.) – Timer Peripherals (PWM, MIOS modules, etc. ) – System Peripherals (IRQ, FMPLL)
Slide 4: Why System Simulation with a Full-Chip-Simulator?
4 Why System Simulation with a Full-Chip-Simulator? • Early start of SW development, e.g. lowlevel driver, SW integration, etc. with respect to hardware • Early start of control algorithm implementation • Software profiling, cycle accurate performance estimation • Platform for future architecture an
Slide 5: Use Cases for Simulators
5 Use Cases for Simulators Pre-Silicon Silicon Exists Abstraction System System Evaluation (Performance) System Debug Rapid Prototyping on System Level System Evaluation (Performance) Level Software Methods Verification System Modification for Future System Architectural Analysis Device Software Dev
Slide 6: HCS12 Simulator Features
6 HCS12 Simulator Features • HCS12 Core and memory models • Peripheral model simulation (Flash, RAM, MMC, CRG, IRC, A/D, PWM, etc. ) • Fast C/C++ Models, High Simulation Speed • Clock Cycle Count Accurate • I/O File Dump and Stimuli, (single signals, bus trace, token) • Additional Debug Capability t
Slide 7: HCS12 - Saber Co-Simulation
7 HCS12 - Saber Co-Simulation • Demonstration model of a “speed control system” • Closed Loop via A/D converter and PWM • Co - Simulation through sockets • Tools Required – Metrowerks Codewarrior IDE for HCS12 – Saber • HCS12 ISS Model integrated in Codewarrior IDE • Peripherals modeled: RAM, Flash,
Slide 8: Simulation Backplane
8 Star12 System Simulator Demo Architecture • Co-Simulation via Sockets HiWave • Separate Start-up Debugger • Lock-step Synchronization • SABER Master – Star12 Slave HCS12 Core Platform Simulation Backplane SABER RAM, Flash, EEPROM, Socket CRG, IRQ, A/D Converter Circuit Model Circuit Model PWM Circ
Slide 9: Speed Control System
9 Speed Control System Saber Schematic Motor Application Signal Co-Simulation Adaptation interface to HCS12 SNUG Saber 2002 9
Slide 10: CodeWarrior HCS12
10 CodeWarrior HCS12 Development Suite Source code debugging CPU Registers Simulator Console Memory map Variable Window access SNUG Saber 2002 10
Slide 11: Simulation Results
11 Simulation Results Stimuli, Response Graph0 (rad/s) : t(s) 5.0 2000.0 shaft (-) : t(s) 4.0 speed_ref 1500.0 3.0 1000.0 2.0 500.0 1.0 0.0 0.0 0.0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0 3.25 3.5 3.75 4.0 t(s) SNUG Saber 2002 11
Slide 12: Summary
12 Summary • Using a virtual prototype of the HW system as basis for software development & validation • Potentially ahead of silicon • Superior debugging capabilities and better observability than traditional methods (e.g. in-circuit emulation or evaluation boards) • Software-in-the-Loop developmen
Slide 13: Outlook
13 Outlook • Performance Improvements by: – Optimized synchronization and communication – Exploiting capabilities of Calaveras Algorithm – Improved models by taking knowledge about semantics into account ➢ A/D conversion resolution ➢ PWM synchronous events • Running Saber as a slave of the Full Chip