ASML Holding NV · EURONEXT:ASML
ASML Holding NV — DB 2014 TMT Conference
22 slides from ASML Holding NV's conference presentation, Sep 4, 2014
Slide 1: EUV – Supporting Moore's Law
EUV – Supporting Moore’s Law Marcel Kemp Director Investor Relations - Europe DB 2014 TMT Conference London September 4, 2014
Slide 2: Forward looking statements
Forward looking statements Public Slide 2 Sep 4, 2014 This document contains statements relating to certain projections and business trends that are forward-looking, including statements with respect to our outlook, expected customer demand in specified market segments, expected sales levels, system
Slide 3: Content
Content Public Slide 3 Sep 4, 2014 • Semiconductor environment • Challenges of shrink • Our response: the lithography roadmap
Slide 4: Net Sales
Total net sales M€ by End-use Public Slide 4 Sep 4, 2014 6000 5,651 5,245 767 5000 4,732 4,508 Memory 1,252 IDM 613 930 Foundry 4000 3,768 1,856 YTD Service & Options 417 Net Sales 944 3,040 2,954 3000 487 2,064 437 366 2,279 767 570 844 358 2000 473 698 1,596 440 526 421 2,585 2,294 588 1000 315 2,
Slide 5: Business environment
Business environment Public Slide 5 Sep 4, 2014 • The ramp of the 20/16/14 nm nodes is set to continue, however as we discussed last quarter some customers continue to evaluate the timing of their litho deliveries to synchronize supply and demand, leading to an adjustment of the ASML Q4 shipment for
Slide 6: The rise of smart phones and tablets
The rise of smart phones and tablets Public Longer term Logic growth Slide 6 Sep 4, 2014 Source: Pablo Temprano, Samsung, ISS Jan 2014
Slide 7: Product trends and memory market evolution
Product trends and memory market evolution Public Memory growth Diversification in the memory market Slide 7 Sep 4, 2014 PC Mobile Big Data W/W Memory Revenue ($B) Enterprise Mobile DRAM PC SSD NAND PC DRAM 1985 1990 1995 2000 2005 2010 2015 Source: Pablo Temprano, Samsung ISS, Jan 2014
Slide 8: Challenges of shrink
Content Public Slide 8 Sep 4, 2014 • Semiconductor environment • Challenges of shrink • Our response: the lithography roadmap
Slide 9: No end in sight for logic scaling
Bulk CMOS:100nm gate length Public No end in sight for logic scaling Slide 9 Sep 4, 2014 N20 N20 / N14 N1x / N7 N7 / N5 N5 / N3.5 Bulk CMOS: SOI: Bulk FinFet : SOI FinFet : Gate-all-around Complementary Silicon on Insulator Fin field effect Silicon on insulator transistor Metal Oxide transistor fin
Slide 10: Our response: the litho roadmap
Content Public Slide 10 Sep 4, 2014 • Semiconductor environment • Challenges of shrink • Our response: the litho roadmap
Slide 11: Our Challenge: enable affordable scaling
Our Challenge: enable affordable scaling Public Slide 11 Sep 4, 2014 • Scaling needs to create lower cost and improved performance – ie., support Moore’s Law • Affordable scaling in lithography can be achieved: • In the near term - Immersion: drive productivity and yield (overlay and focus control)
Slide 12: Affordable shrink roadmap
Affordable shrink roadmap Public Slide 12 Sep 4, 2014 2012 2013 2014 2015 2016 2017 2018 2019 2020 Immersion OVERLAY : DCO 2.5 nm <1.0 nm NXT:1950i, NXT:1960Bi, IMAGING : CDU 2.0 NXT:1970Ci nm 0.6 nm THROUGHPUT : 230 wafers per hour (wph) >250 wph Supported by a Holistic Lithography approach u
Slide 13: Today immersion extensions at 10 nm node possible with 1D
Today immersion extensions at 10 nm node possible with 1D But critical metal layers require extra wiring layers, adding processing complexity Public Slide 13 and cost; decreasing chip performance Sep 4, 2014 Longer routing and more vias increase resistance and affect performance 2 extra wire distrib
Slide 14: Cost: 1D/immersion vs 2D/EUV
Cost: 1D/immersion vs 2D/EUV Public Slide 14 Sep 4, 2014 Critical metal cost/immersion Patterning cost per flop/immersion normalized to N20/N16 Critical metal 1D density Patterning cost Moore's law requires extra layers, results in steep cost increase 1 Shrink is possible with 1D The flip flop is a
Slide 15: Cost: 1D/immersion vs 2D/EUV
Cost: 1D/immersion vs 2D/EUV Public Slide 15 Critical metal cost/immersion Sep 4, 2014 Critical metal cost/EUV Patterning cost per flop/immersion normalized to N20/N16 Patterning cost per flop/EUV 2D EUV: critical Patterning cost Moore's law metal cost dramatically reduced 1 Staying with 2D designs
Slide 16: EUV technology roadmap - extendibility to <7nm
EUV technology roadmap - extendibility to <7nm (half pitch) > 5x node generations Public Slide 16 Sep 4, 2014 Half pitch Under study Resolution [nm] 32 27 22 16 13 10 7 <7 Wavelength [nm] layo13.5 Lens NA 0.25 ut 0.33 0.33NA DPT >0.5NA Illumination coherence s=0.5 s=0.8 s=0.2-0.9 Flex-OAI Extended
Slide 17: EUV: Evaluations for 10nm process insertion underway
EUV: Evaluations for 10nm process insertion underway Public Slide 17 Sep 4, 2014 Large vacuum chamber New light source Mirror optics
Slide 18: What did we achieve since last year?
What did we achieve since last year? Public Slide 18 Sep 4, 2014 EUV meets aggressive 2D Good Matched Machine Full size free-standing pSi logic imaging Overlay performance proto-type pellicle realized requirements Without pellicle With pellicle 31nm 22nm 16nm Full wafer MMO CD map (nominal CD map (n
Slide 19: Progress on all areas to improve system productivity
Progress on all areas to improve system productivity Public Slide 19 Sep 4, 2014 Conversion Automation efficiency Collector protection System Availability Drive laser • Full automation Source Power power plasma control with • Higher conversion Droplet good dose control efficiency generator demonstra
Slide 20: EUV status at customers: Towards production insertion
EUV status at customers: Towards production insertion Public For process development, customers typically require 100 wafers per day. Slide 20 Sep 4, 2014 For pre-production customers have asked us to deliver 500 wafers per day by the end of 2014. • 2014 Q1 : 100 wafers per day √ • Q2 : 200 wafers p
Slide 21: Summary: EUV towards production insertion
Summary : EUV towards production insertion Public Slide 21 Sep 4, 2014 Multiple customers are qualifying EUV for insertion at the N10 nm logic node Imaging and overlay is in line with requirements for N10 insertion Defect reduction ~10x per year shown and full-size EUV pellicle prototype manufacture
Slide 22: ASML
ASML