Vicor Corporation · NASDAQ:VICR

Vicor — EEHE 2023

20 slides from Vicor's conference presentation, June 2023

  1. Slide 1: Managing high-voltage line ripple rejection using high bandwidth DC-DC

    Managing high-voltage line ripple rejection using high bandwidth DC-DC Haris Muhedinovic EEHE, June 2023, Essen, Germany

  2. Slide 2: Electric vehicle HV bus overview and inverter ripple

    Electric vehicle HV bus overview and inverter ripple High voltage ripple occurs on high voltage bus during propulsion and regeneration as a result of inverter’s (PIM) operation Most of the ripple is filtered by inverter’s bulk capacitor but significant part is injected to HV bus and can cause issues

  3. Slide 3: Impact of inverter ripple on DC-DC converter

    Impact of inverter ripple on DC-DC converter n Component degradation: – DC-DC input filter capacitors are exposed to both DC-DC switching current and inverter ripple – Self-heating caused by (𝐼!"# $ 𝑅 %&' ) leads to component degradation n Ripple transfer to DC-DC output – DC-DC closed-loop…

  4. Slide 4: Resonances: HVPM HVDC Filters

    Resonances: HVPM HVDC Filters HVDC filters are designed to address EMI noise and not inverter ripple. If designed without taking inverter ripple into consideration, the filter can inadvertently be excited by inverter ripple

  5. Slide 5: Ripple rejection – Example

    Ripple rejection – Example HV Ripple: Frequency = 2kHz Magnitude = 19Vp-p Converter Voltage Ripple Magnitude: 0.7 Vp-p HV Ripple: Frequency = 4kHz Magnitude = 20Vp-p Converter Voltage Ripple Magnitude: 1.14 Vp-p HV Ripple: Frequency = 10kHz Magnitude = 23Vp-p Converter Voltage Ripple Magnitude: 1.7

  6. Slide 6: Solutions to address inverter ripple

    Solutions to address inverter ripple n Minimize inverter ripple on HV bus: – Modify drive profiles – Increase DC link capacitance – Implement “No-fly” zones to avoid exciting component resonances n Design converters which operate significantly higher above potential oscillations (ripple) on HV bus.

  7. Slide 7: High frequency, soft switching DC-DC and impact on EMI filter

    High frequency, soft switching DC-DC and impact on EMI filter n Increased power density n Minimized voltage and current ripple n Minimized EMI filtering effort n Closed loop control bandwidth extended

  8. Slide 8: Example/filter design: Design steps

    Example/filter design: Design steps 1. Select the cut-off frequency below the crossover frequency of the converter 2. Choose the inductor L based on maximum input current, calculate C based on equation or determine C based on voltage level and calculate L 3. Select appropriate filter network and cal

  9. Slide 9: Filter comparison

    Filter comparison 5kHz cut-off 25kHz cut-off

  10. Slide 10: Filter Comparison – applying ripple voltage on HV input bus

    Filter Comparison – applying ripple voltage on HV input bus 5kHz cut-off 25kHz cut-off

  11. Slide 11: Filter output impedance

    Filter output impedance In order to keep filter losses lower, output impedance of the high cut-off filter should be below output impedance of the low cut-off, until frequency of interest Lower impedance – lower losses, break even point 16kHz

  12. Slide 12: Size comparison – for filters with equal power losses

    Size comparison – for filters with equal power losses L1= 20 x L10 C4= 50 x C17 To keep losses equal and distributed ONLY EXAMPLE

  13. Slide 13: Filter topology influence

    Filter topology influence n Undamped filter Series damped might be – Risk of uncontrolled voltage amplification more attractive due to – Avoid inverter switching frequency lower current at high n Simplified damped voltage level. – Weak attenuation at higher frequencies Relative size ratio will n Ser

  14. Slide 14: Vicor's DC-DC converter under HV ripple – time domain

    Vicor’s DC-DC converter under HV ripple – time domain VIN = 700 + 20*sin(2*pi*2k*t)

  15. Slide 15: Vicor's DC-DC converter under HV ripple – time domain

    Vicor’s DC-DC converter under HV ripple – time domain VIN = 700 + 20*sin(2*pi*10k*t)

  16. Slide 16: Vicor's DC-DC converter under HV ripple – time domain

    Vicor’s DC-DC converter under HV ripple – time domain VIN = 700 + 20*sin(2*pi*17k*t)

  17. Slide 17: Vicor's DC-DC converter under HV ripple – frequency response

    Vicor’s DC-DC converter under HV ripple – frequency response

  18. Slide 18: Conclusion

    Conclusion Vicor DC-DC converter enables: n Highest power density conversion n Smallest EMI filter (high switching frequency and ZVS/ZCS topology) – Shifting frequency range n Reliable system and simplified architecture n High frequency enable higher closed loop bandwidth and rejects inverter ripple

  19. Slide 19: Haris Muhedinovic

    Haris Muhedinovic Principal Application Engineer hmuhedinovic@vicr.com +49 171 5647279 ©2023 Vicor 19

  20. Slide 20: Thank you

    Thank you Scan and download the presentation ©2023 Vicor 20

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