Sitime Corporation · NASDAQ:SITM
Sitime — Technical Presentation (September 2012)
11 slides from Sitime's technical presentation, Sep 19, 2012
Slide 1: Enhance FPGA-based Systems with Programmable Oscillators
Enhance FPGA-based Systems with Programmable Oscillators Sassan Tabatabaei Director, Strategic Applications SiTime Corporation ESC- ESC-3027 Outline •FPGA clocking •Programmable clocks •Dynamic programmable oscillators •EMI reduction •Conclusions SiTime Corporation, www.sitime.com 2
Slide 2: FPGA Clocking and Clocking Speed
FPGA Clocking •FPGA designs use multiple clocks to drive different blocks –Each may require a different frequency •External and internal clocks –Dependent on clock speed and jitter requirements SiTime Corporation, www.sitime.com 3 Clocking Speed • Multiple standard frequencies for different applicat
Slide 3: Typical Integer PLL and PLL Bandwidth
Typical Integer PLL f in f out Output frequency is defined by Equation 1: f M f out = in P N SiTime Corporation, www.sitime.com 5 PLL Bandwidth •Maximum PLL bandwidth is a f in function of phase detector BWPLL < 10P update rate f in •More practical limit: BWPLL < 20P •Large P à
Slide 4: Optimizing PLL Design
Optimizing PLL Design • Programmable oscillator as an external reference – Lower demand on the internal PLL f BWPLL < in 10P – High frequency resolution • Reduce required pre-divide ratios • Higher PLL bandwidth – Low jitter SiTime Corporation, www.sitime.com 7 Optimizing PLL Design 1 MHz f in = 25
Slide 5: EMI Reduction in FPGA Devices
EMI Reduction in FPGA Devices •Edge rate tuning with programmable oscillators –Increase the rise and fall time of the clock signal –Reduces EMI generated by higher order clock harmonics radiated from the clock traces in a specific circuit –The peak clock signal remains constant, avoiding the voltage
Slide 6: Rise/Fall Time Control and Spread-spectrum Clocking
Rise/Fall Time Control for EMI Reduction • Edge rate adjustment methods – Increase load capacitance • Increases current consumption – Adjusting output current drive with programmable oscillators • Does not affect current consumption • Drive strength tuning for EMI reduction – Only works on one circu
Slide 7: SSC Modulation to Reduce EMI; In-system Frequency Programming
SSC Modulation to Reduce EMI 15 10 1 0 2 3 -1 0 CLK without spread -2 0 CLK w/ down spread - 2% -3 0 EMI Reduction 14.90 dB -4 0 -6 0 -5 0 -7 0 -8 0 -8 5 SiTime Corporation, www.sitime.com 13 In-system Frequency Programming • Digitally controllable oscillators (DCXOs) – Superior frequency control –
Slide 8: Quantization-induced Phase Noise; Update Rate Effect
Quantization-induced Phase Noise Update rate of 25 kHz for DCXOs with different frequency resolutions SiTime Corporation, www.sitime.com 15 Update Rate Effect on Phase Noise • Typically, low update rates causes error signals from the phase detector and loop filter to be integrated by the DCXO over a
Slide 9: Update Rate Effect on Phase Noise; Jitter Clean-up
Update Rate Effect on Phase Noise DXCO with 1 ppb frequency resolution SiTime Corporation, www.sitime.com 17 Jitter Clean-up • Jitter clean-up techniques needed when locking to a noisy system clock to generate a stable clock signal with low phase noise and low jitter • High precision oscillators for
Slide 10: FPGA and DCXO Jitter Cleaner; Conclusion
FPGA and DCXO Jitter Cleaner FPGA F_in Digital phase (from netwrok, Loop filter detector DCXO etc.) (Digital) (PD) ÷N SiTime Corporation, www.sitime.com 19 Conclusion •Programmable oscillators add flexibility and performance to FPGA-based systems •EMI control with rise/fall adjustment and SSC •FPGA
Slide 11: Timing Topics at Design East; Contact SiTime
Timing Topics at Design East • Clock Architectures and their Impact on System Performance and Reliability – Session Code: ESC-2001 – Track: Analog & Mixed Signal Design – Date/Time: 9/18/2012, 8:00:00 - 9:15:00 AM – Location: 202 • How Environmental Forces Impact System Reliability – Session Code: E