Applied Materials, Inc. · NASDAQ:AMAT
Applied Materials — Investor Day (June 2021)
68 slides from Applied Materials's investor day presentation, Jun 16, 2021
Slide 1: Logic Master Class
LOGIC MASTER CLASS JUNE 16, 2021
Slide 2: Forward-Looking Statements and Other Information
Forward-Looking Statements and Other Information Today’s presentations contain forward-looking statements, including those regarding anticipated growth and trends in our businesses and markets, industry outlooks and demand drivers, technology transitions, our business and financial performance and m
Slide 3: Welcome
2021 Master Classes WELCOME Michael Sullivan CVP, Head of Investor Relations LOGIC MASTER CLASS | June 16, 2021 Applied Materials External Use
Slide 4: Upcoming Investor Events
UPCOMING INVESTOR EVENTS MASTER CLASSES June Second Half 16 2021 Logic Specialty semiconductors Heterogeneous design and advanced packaging Inspection and process control Applied Materials External Use
Slide 5: Upcoming Investor Events
UPCOMING INVESTOR EVENTS MASTER CLASSES June September October 16 8* 18* Logic ICAPS Process & Control Advanced & Packaging AIx ™ Platform * Projected Dates Applied Materials External Use
Slide 6: Agenda
AGENDA 9:00 PART 1 HOST: Mike Sullivan Logic Thesis Fireside Chat | PR Chidi Chidambaram, Ph.D., Qualcomm 9:15 PART 2 HOST: Uday Mitra, Ph.D. Logic Technology Transistor | Michael Chudzik, Ph.D. Interconnect | Mehul Naik, Ph.D. Patterning & DTCO | Regina Freed 9:55 PART 3 HOST: Raman Achutharaman, P
Slide 7: Takeaway Messages
TAKEAWAY Messages 1. “AI Era”= Secular growth in logic capacity 2. PPACt™ enablement via the New Playbook will capture a growing proportion of WFE market growth 3. DTCO is a powerful way to use materials engineering to drive continued 2D scaling at existing line widths * Free cash flow = operating c
Slide 8: Semi Growth No Longer Limited by Human Consumption
Data Generation By Category (ZB) 157 2018 AUTOMOTIVE MACHINE > HUMAN HOME IOT CROSSOVER DATA-CENTRIC WORLD 92 APP-CENTRIC WORLD INDUSTRIAL IOT 55 30 13.8 6.6 0.1 0.3 0.8 1.6 3.1 HUMAN 2015 2016 2017 2018 2019 2020 2021E 2022F 2023F 2024F 2025F SEMI GROWTH NO LONGER LIMITED BY HUMAN CONSUMPTION Sourc
Slide 9: Silicon Content Growing as Everything Gets Smarter
Semi content per unit 2015 2020 2025F HIGH END SMARTPHONE $100 $170 $275 +62% AUTO (GLOBAL AVERAGE) $310 $460 $690 +50% DATACENTER SERVER (CPU + ACCELERATOR) $1,620 $2,810 $5,600 +99% SMARTHOME (GLOBAL AVERAGE) $2 $4 $9 SILICON CONTENT GROWING AS EVERYTHING GETS SMARTER Source: Applied Materials App
Slide 10: Strong Multiyear Capital Investments
Strong Multiyear Capital Investments “TSMC to Spend $100 Billion Over Three Years to Grow Capacity” – Bloomberg, 3/31/2021 “Intel CEO Presses Turnaround Effort With $20 Billion Investment Plan” – The Wall Street Journal, 3/23/2021 “Samsung to Invest $115 Billion in Foundry & Chip Businesses by 2030”
Slide 11: Incentives for Domestic Production
Incentives for Domestic Production “Biden doubles down on a $50 billion plan to invest in chips” – Fortune, 4/13/2021 “EU aims to be independent chip power with 20% global share” – Nikkei Asia, 3/10/2021 “South Korea joins global chipmaking race with $450 billion spending plan” – Fortune, 5/13/2021
Slide 12: Playbook and Growth Drivers
Playbook and Growth Drivers New architectures/ Specialty devices, mature nodes (IoT), custom ASIC New devices New structures/3D Future 3D devices favoring our served markets ’20 to ’24 PERFORMANCE New materials Low resistance metals, high-speed DRAM periphery Rev oppty. +$7B Rev CAGR 13% POWER AREA-
Slide 13: Industry Papers Discuss PPACt and DTCO
Industry Papers Discuss PPACt™ and DTCO Abstract: “This IC technology scaling is driven by key factors such as performance, power, perfection (yield/reliability), area, cost, and time to market (PPACt)” ISSCC, February 15, 2021 “Unleashing the Future of Innovation” Dr. Mark Liu, Chairman, TSMC Abstr
Slide 14: Logic Technology
PART 2 Logic Technology Uday Mitra, Ph.D. Vice President Semiconductor Products Group LOGIC MASTER CLASS | June 16, 2021 Applied Materials External Use
Slide 15: Enabling PPACt Roadmap for Logic
Enabling PPACt™ Roadmap for Logic FinFET Scaled FinFET GAA FOUNDRY NODE 14/16nm 10/7nm 5nm 3nm 2nm < 2nm 2015 2017 2019 2021 2023 2025+ CHANNEL STI Optimization Epi SiGe Channel Epi Si / SiGe SL SD Epi SiAs+SiP Inner Spacer GATE Conformal HKMG Band-Edge New Dipole CONTACT Co fill Sel W MOL Liner-fre
Slide 16: Part 2: Logic Technology
PART 2 LOGIC TECHNOLOGY TRANSISTOR INTERCONNECT PATTERNING & DTCO Michael Chudzik, Ph.D. Mehul Naik, Ph.D. Regina Freed Vice President of Technology Managing Director and Principal Managing Director of Member of our Technical Staff Patterning Technology Applied Materials External Use
Slide 17: Logic Transistor Challenges and Roadmaps
PART 2 Logic Transistor Challenges and Roadmaps Michael Chudzik, Ph.D. Vice President Semiconductor Products Group LOGIC MASTER CLASS | June 16, 2021 Applied Materials External Use
Slide 18: Zooming in on Smartphone Chip Transistors
Zooming in on Smartphone Chip Transistors 5nm technology node >11.8 billion transistors >24 billion contacts Source: Apple Processor chip: 88mm2 size 7 threshold voltages 8.57 mm x 10.23 mm HPC and mobile compute Source: TechInsights Source: Apple Microscope cross section view of chip 3D model of a
Slide 19: Decades of Leadership in Transistor Enablement
Decades of Leadership in Transistor Enablement Selective Epi High-k Metal Gate FinFET Advanced FinFET Gate-All-Around 2002 2007 2012 2020 2023 Epi Implant Integrated Unit Metal Gate Materials Process RTP Anneal Solutions Leadership CMP Leadership Selective Removal Applied Materials External Use
Slide 20: Physics of Transistor Performance
Physics of Transistor Performance Transistor performance Scaling implication Variability implication Gate length 1 (Lg) Transistor speed = Gate Higher 𝑡𝑡 average speed 𝐶𝐶𝐶𝐶 Delay t = = 𝐶𝐶𝑅𝑅 Slowest Slowest 𝐼𝐼𝑑𝑑 Fin height blue red (Hfin) 𝐻𝐻𝑓𝑓𝑓𝑓𝑓𝑓 𝜇𝜇 𝐼𝐼𝑑𝑑 ≈ 𝑉𝑉𝐺𝐺 −…
Slide 21: Transistor Scaling Modules and Approaches
Transistor Scaling Modules and Approaches Module Scaling levers Channel isolation 1 Channel and trench High AR / taller and thinner fins isolation Higher mobility SiGe channel Tox scaling 2 High-k metal gate VT tuning – metal gate 2 3 1 Source drain engineering 3 Transistor source & drain resistance
Slide 22: Transistor Scaling: Channel and Trench Isolation Module
Transistor Scaling: Channel and Trench Isolation Module Inflections 1st generation FinFET Scaled tall FinFET New materials SiGe 2012 2017 2020 Scaling lever High value problems Solutions Co-optimized trench isolation fill Scaled tall FinFET Bending of high aspect ratio fins Flowable oxide fill, impl
Slide 23: Channel and Trench Isolation Formation
Channel and Trench Isolation Formation Increasing fin height and aspect ratio Managing fin bending through co-optimized processes ~7:1 ~6:1 ~5:1 ~3:1 Fin bending 47% VT variability 30% Drive current Id 5% Gen 1 Gen 2 Gen 3 Gen 4 Baseline Improved Higher aspect ratio fins have worse fin bending Bent
Slide 24: Transistor Scaling: High-k / Metal Gate Module
Transistor Scaling: High-k / Metal Gate Module Gate oxide scaling tox scaling boosts Ion Interfaces very critical suppresses Ioff and 𝑡𝑡𝑜𝑜𝑜𝑜 Si Fin How we treat improves transistor control How we terminate Interface Metal gate Metal gate VT tuning Transistor can be tuned and high-k stack Band…
Slide 25: Transistor Gate Oxide Scaling with Co-Optimization
Transistor Gate Oxide Scaling with Co-Optimization High value problem Solution Conventional process Wet chemical oxide IMS gate stack module Interface layer Not integrated Treatments Interface / Materials engineering Treatments ALD High-k Integrated processes ALD High-k Gate oxide scaling has slowed
Slide 26: Tuning Transistor Performance with Metal Gate
Tuning Transistor Performance with Metal Gate Multiple VT flavors for different device types VT tuning methods ❶ Thickness modulation HPC platform for high performance eLVT MG ALD work function metal gate layer Stand-by Power Psb(uW) uLVT HK/IL ALD and etch modulate thickness N5 HPC LVT SVT SVT
Slide 27: Transistor Scaling: Transistor Resistance
Transistor Scaling: Transistor Resistance Transistor resistance High value problem Rplug 7% X10-11 Contact Area = Fin Pitch x Contact Length Rplug 2 Rexternal 44% Published Hardware Contact Area [cm2] ITRS Roadmap 1.5 Rinterface 7nm 1 5nm Rexternal 3nm Rchannel Rinterface 49% 0.5 0 30 40 50 60 70 80
Slide 28: Transistor Scaling: Source/Drain Resistance
Transistor Scaling: Source/Drain Resistance Transistor resistance High value problem 1 Incoming 2 Lateral Etch Highly selective lateral etch to avoid spacer Rplug loss and optimal cavity profile control Rinterface Producer® Siconi™ and Selectra® with >100:1 Rexternal selective etch Rchannel 3 Epi Si
Slide 29: Levers for Logic Scaling: New Architecture
Levers for Logic Scaling: New Architecture High value problem Solution: Gate-All-Around (GAA) Critical FinFET dimensions Variation in critical dimensions FinFET GAA 8.8nm 6.3nm 7.2nm 7.5nm Wfin Hfin Lg Wfin Wfin 90o THK TIL 14 10 7 5* 3* Source: Chipworks Node (nm) 𝐻𝐻𝑓𝑓𝑓𝑓𝑓𝑓 𝜇𝜇 𝐼𝐼𝑑𝑑 ≈…
Slide 30: Gate-All-Around: Process Flow
Gate-All-Around: Process Flow Key new module steps Requirements ① Super lattice epitaxy Sharp interfaces, thickness control ② Selective removal Etch selectivity, no nanosheet collapse Metal gate Si ③ S/D stressors (etch, epitaxy) Controlled recess & growth 6 1 3 2 4 5 ④ Inner spacer (sel. removal, d
Slide 31: Gate-All-Around: Superlattice Epitaxy and Removal
Gate-All-Around: Superlattice Epitaxy and Removal High value problem ① Si/SiGe superlattice formation Optimized process for Si/SiGe interface and stack uniformity Si SiGe Si Centura® Prime® Epi SiGe /Si epitaxy SiGe Si SiGe ② Si channel release SiGe:Si removal selectivity of >500:1 Optimal edge prof
Slide 32: Gate-All-Around: HKMG & Inner Spacer Modules
Gate-All-Around: HKMG & Inner Spacer Modules High value problem ④ Inner spacer formation Inner spacer Tunable SiGe : Si selectivity for best- in-class recess uniformity ALD spacer deposition Producer® Selectra® selective etch Selective SiGe removal ALD spacer deposition Uniform SiGe lateral push amo
Slide 33: Logic Contact and Interconnect Challenges and Roadmaps
PART 2 Logic Contact and Interconnect Challenges and Roadmaps Mehul Naik, Ph.D. Managing Director Semiconductor Products Group LOGIC MASTER CLASS | June 16, 2021 Applied Materials External Use
Slide 34: Zooming in on Smartphone Chip Interconnects
Zooming in on Smartphone Chip Interconnects >15 layers stacked copper interconnects >24 billion contact trench and via connections Source: Apple Processor chip: 88mm2 size 8.57 mm x 10.23 mm >11.8 billion Source: TechInsights transistors Source: Apple Microscope cross section view of chip 3D model o
Slide 35: Scaling Implication on Interconnect Performance
Scaling Implication on Interconnect Performance CMOS device components Contact plug resistance Interconnect via resistance Reduces drive current Increases dynamic power dissipation MOL via Contact plug resistance (a.U.) Contact Via resistance (a.U.) Line metal >15 layers of >4x >10x Via Copper Inter
Slide 36: Scaling of Contact and Interconnect
Scaling of Contact and Interconnect Scaling challenge Key modules State-of-the-art Inflections Sel W Co contact Liner-free Transistor resistance Contact with liner contact fill reduction Middle of line (MOL) Copper with Copper with Cu conformal Cu selective RC delay and ALD barrier ALD barrier Inter
Slide 37: Contact: Innovations Enable Metal Fill Without Liners
Contact: Innovations Enable Metal Fill Without Liners CD shrink + liner = high R, rc Contact resistance throttles transistor Thinner/ no liner & low R metal for performance improved performance & yield W with Sel W 1 liner No liner MOL via Contact Plug Resistance (a.u.) W with Co with thick TiN W co
Slide 38: Selective W Contacts Delivers Lower Power
Selective W Contacts Delivers Lower Power W fill W nucleation layer Contact resistance Conventional TiN liner/barrier Approach 75% of volume consumed by high resistance materials ~40% W fill Conventional Selective W Endura® Volta® Selective W No extra liners or nucleation layers At fixed frequency 1
Slide 39: Levers for Interconnect Scaling
Levers for Interconnect Scaling Scaling challenge State-of-the-art Inflections Copper with Copper with conformal ALD barrier selective ALD barrier RC delay and Cu Cu Higher modulus power consumption low-k films reduction Contributing factors High value problems Solutions Interconnect (Via) High inte
Slide 40: Interconnect Via Resistance Scaling Solutions
Interconnect Via Resistance Scaling Solutions High value problem Solution Conventional: low conductivity interface layers Selective ALD barrier: deposit on dielectric and not on Cu Cu-Liner-Barrier Cu-Liner-Barrier Line Line 32Ω 28Ω Barrier No barrier on Cu Via Via on Cu Liner 19Ω Liner 15Ω Line Lin
Slide 41: All 7 Steps in Vacuum Unique to Applied
PVD INTEGRATED SOLUTIONS ALD 5 CVD 6 PVD Reflow 7 PVD Reflow On-board Metrology 4 ALD ALD 3 1 2 Treat ALD All 7 steps in vacuum unique to Applied Applied Materials External Use
Slide 42: Applied's Unique Solution Lowers Interconnect Resistance
Applied’s Unique Solution Lowers Interconnect Resistance Then Now Selective barrier process 1/2000th human Cu hair Line Applied’s Via Resistance (a.u.) Via low R solution Cu Line 60nm 15nm critical width 7nm 5nm 3nm With Sel Barrier 3 7 # process steps 2 4 # materials conventional selective processe
Slide 43: Dielectric Solutions to Sustain Capacitance Scaling
Dielectric Solutions to Sustain Capacitance Scaling High value problem Solution Low-k pattern integrity for small features Next-gen Black Diamond® (BD) films: higher mechanical strength Larger Metal levels > M5 Modulus (GPa) Next-gen BD Up to 40% higher modulus Metal levels Conventional at the same
Slide 44: PPACt Limitations of Power Delivery Architecture
PPACt™ Limitations of Power Delivery Architecture Cell area scaling challenges Power delivery losses (voltage drop) Gate Power CMOS top metal rail Target drop margin is ~10% in power delivery network Metal track Cell length Voltage drop Voltage CMOS source die Large drop from 12+ levels due to metal
Slide 45: Power Rail Inflection: Backside Power Delivery
Power Rail Inflection: Backside Power Delivery Conventional Buried power rail with backside PDN Power delivery 1.7 to 7x Voltage reduction PPACt Power and Signal lines Benefits 20 to 33% Signal lines cell area reduction Power rail Power rail Transistor Si Power µ-TSV lines High AR power rail fill Si
Slide 46: Logic Patterning and DTCO Challenges and Roadmaps
PART 2 Logic Patterning and DTCO Challenges and Roadmaps Regina Freed Managing Director Semiconductor Products Group LOGIC MASTER CLASS | June 16, 2021 Applied Materials External Use
Slide 47: Two Approaches Enable Logic Cell Area Reduction
Two Approaches Enable Logic Cell Area Reduction Critical parameters in transistor density scaling ❶ Traditional scaling via pitch reduction Contacted gate pitch (CGP) Contact Metal pitch Shrink every feature uniformly Metal ❷ Design and Technology Co-Optimization (DTCO) Gate Simple logic unit cell:
Slide 48: Logic Pitch Scaling Challenges
Logic Pitch Scaling Challenges Size variation across features Variation within a feature Stochastic defects Variation as % of CD LER as % of CD Defects per cm2 > 2x > 2x > 10x Node 10nm 7nm 5nm 3nm Node 10nm 7nm 5nm 3nm Node 10nm 7nm 5nm 3nm open LER short Variation increasing in local and Line edge
Slide 49: Innovations to Enable Low Variability EUV Etch Process
Innovations to Enable Low Variability EUV Etch Process Higher selectivity CVD hardmask + Advanced etch and deposition capability Incoming CD More dep in wide Dep-etch After etch variation CD areas cycling CD Bias reduced N In-situ deposition with advanced pulsing for better profile and CD uniformity
Slide 50: Patterning Defect Reduction with Co-Optimization
Patterning Defect Reduction with Co-Optimization Key challenges in EUV patterning Enabling improved CD uniformity and defect performance LCDU LER Opens 50% 30% 99.8% open LER short Pre Post Pre Post Pre Post Local and across-wafer CD uniformity Line Edge Roughness Co-optimized dep-etch processes wit
Slide 51: Cost-Effective and Reduced Variability Patterning Solution
Cost-Effective and Reduced Variability Patterning Solution Conventional hardmask Conformal CVD hardmask Conventional EUV SADP New materials with co-optimization Patterning films Spin-on and furnace High quality CVD films – DARC®, APF® # of layers 5 3 Co-optimization Required CVD co-optimized with Sy
Slide 52: DTCO Enabled by Materials Engineering Portfolio
DTCO Enabled by Materials Engineering Portfolio Example of DTCO: Self Aligned Diffusion Break Scaling the Diffusion Break Gate Diffusion Breaks Single Break Fin Diffusion Breaks Self Aligned Diffusion Break 15% horizontal scaling by reducing the CGP grid High aspect ratio, small width Requirement: h
Slide 53: Future DTCO Modules for Logic Scaling
Future DTCO Modules for Logic Scaling Buried power rail with backside PDN Power Signal rail lines Power rail moved below transistors Power rail Signal Transistor lines Si Fin Power µ-TSV lines Power rail Gate Power delivery 20 to 33% cell area reduction with benefit of performance gains Enabled by a
Slide 54: Future of Logic Scaling
Future of Logic Scaling Scaling lever Current Inflections Pitch and DTCO scaling Intrinsic scaling DTCO Pitch scaling EUV + Material engineering to improve EUV SADP variability and reduce process steps >50% >40% >25% 1% DTCO 16nm 10nm 7nm 5nm 3nm Source: M. Liu/tsmc, ISSCC 2021 Pitch reduction Scali
Slide 55: Logic Opportunities and Momentum
PART 3 Logic Opportunities and Momentum Raman Achutharaman, Ph.D. Group Vice President Semiconductor Products Group LOGIC MASTER CLASS | June 16, 2021 Applied Materials External Use
Slide 56: Playbook and Growth Drivers
Playbook and Growth Drivers New architectures/ Specialty devices, mature nodes (IoT), custom ASIC New devices New structures/3D Future 3D devices favoring our served markets ’20 to ’24 PERFORMANCE New materials Low resistance metals, high-speed DRAM periphery Rev oppty. +$7B Rev CAGR 13% POWER AREA-
Slide 57: Memory Master Class
Memory Master Class Applied Materials External Use
Slide 58: Historical WFE Mix
Historical WFE Mix Foundry / Logic vs. Memory Memory mix consistent over time <45% 10-year and 20-year averages: Foundry / Logic >55% Foundry / Logic >55% Foundry / Logic > Memory in 17 of past 20 years Long-Term Average Source: Gartner, VLSI, Applied Materials Applied Materials External Use
Slide 59: Historical WFE Mix
Historical WFE Mix Trailing Nodes Foundry / Logic vs. Memory Memory mix consistent over time <45% 10-year and 20-year averages: Foundry / Logic >55% Leading Nodes Foundry / Logic 10-year average: Leading nodes ~2/3 Trailing nodes ~1/3 10-Year Average Source: Gartner, VLSI, Applied Materials Appl
Slide 60: ICAPS Focused on Trailing Node Foundry-Logic
ICAPS Focused on Trailing Node Foundry-Logic Applied Materials External Use
Slide 61: Packaging Grows by Enabling Higher Performance
Packaging Grows by Enabling Higher Performance Intel leans hard on advanced chip packaging technologies in battle for computing supremacy SEP 16, 2020 | VENTUREBEAT TSMC and Google look to chip packaging to boost computing power NOV 19, 2020 | TAIWAN NEWS AMD 3D Stacks SRAM Bumplessly JUN 7, 2021 |
Slide 62: Historical WFE Mix
Historical WFE Mix Trailing Nodes Foundry / Logic vs. Memory Memory mix consistent over time <45% 10-year and 20-year averages: Foundry / Logic >55% Leading Nodes Foundry / Logic 10-year average: Leading nodes ~2/3 Trailing nodes ~1/3 10-Year Average Source: Gartner, VLSI, Applied Materials Appl
Slide 63: Foundry/Logic Growth Trends
Foundry/Logic Growth Trends >2.75x growth in spending Logic / Foundry WFE expansion with digital transformation of the global economy Increasing process complexity Leading edge drives 2/3 of Foundry/Logic WFE Year ’16 ’20 ’24F Applied Materials External Use
Slide 64: Enabling the Transistor Roadmap: Gate-All-Around
Enabling the Transistor Roadmap: Gate-All-Around KEY NEW MODULE STEPS REQUIREMENTS ① Super lattice epitaxy Sharp interfaces, thickness control Metal gate ② Selective removal Etch selectivity, no nanosheet collapse 6 Si 1 3 2 5 ③ S/D stressors (etch, epitaxy) Controlled recess & growth 4 SiO2 ④ Metal
Slide 65: Enabling the Interconnect Roadmap
Enabling the Interconnect Roadmap >2X process step growth >3X TAM growth >30 years of PVD market leadership >25,000 Endura® installed base chambers Breakthrough technologies + new materials + unique combinations + interface engineering Delivering node-over-node PPACt™ gains ↓ R, ↓ power, ↑yield, ↑re
Slide 66: Patterning Growth Driven by New Products
Patterning Growth Driven by New Products >$3.5B cumulative revenue next 4 years Successful Sym3® family of etch products >2X growth New materials for hard mask and patterning >2X growth Innovative technologies + acceleration with co-optimization + acceleration with metrology Materials enabled scalin
Slide 67: Applied's eBeam Inspection and Metrology Leadership
Applied’s eBeam Inspection and Metrology Leadership Unique challenges with 3D structures Full wafer statistics needed Driving revenue growth eBeam inspection eBeam metrology 2.6x SiGe remain 1.4x 1.0x In-device CD and overlay Gate-All-Around FY'13-FY'16 FY'17-FY'20 FY'21-FY'24F Finding buried defect
Slide 68: Ul arenas.
Ul arenas. make possible