Cirrus Logic, Inc. · NASDAQ:CRUS
Cirrus Logic — Embedded Processor Forum 2000
16 slides from Cirrus Logic's conference presentation, Jun 13, 2000
Slide 1: Introducing Maverick EP9312
9312 Introducing Maverick EP9312 Jeff Klaas - Director of Engineering Presented at the Embedded Processor Forum San Jose, California, June 13, 2000
Slide 2: Digital Audio Jukebox
9312 Digital Audio Jukebox 2
Slide 3: The Challenge
9312 The Challenge Create a cost-effective solution for a digital audio jukebox meeting the following goals: ➨ Quick time-to-market ➨ 10x Real-time MP3 encoding ➨ Hardware based content security ➨ High-quality audio ➨ Home network enabled ➨ Robust I/O for OEM flexibility ➨ Low cost storage options ➨
Slide 4: The Solution
9312 The Solution Create a cost-effective solution for a digital audio jukebox meeting the following goals: ➨ Quick time-to-market ✔ ARM 920T Core ➨ 10x Real-time MP3 encoding ✔ MaverickCrunchTM Engine ➨ Hardware based content security ✔ MaverickLockTM Security ➨ Low cost storage options ✔ EIDE Cont
Slide 5: Processor Core and User Interface
9312 Processor Core Serial Ports ARM920T Processor ✔ 200 MHz Processor Clock 3 Port USB Ethernet UARTs (3) w/ I2 S MAC SPI ✔ 16KB instruction & data caches Host HDLC ✔ 64 entry instruction & data TLB Bus Interrupts and ✔ Independent lockable pages Bridge GPIO ✔ Windows CE compatible MMU CrunchTM Eng
Slide 6: 9312 MaverickCrunch Engine
TM 9312 MaverickCrunch Engine Serial Ports General Architecture for Market Specific Extensions 3 Port USB Ethernet MAC UARTs (3) w/ I2 S SPI Host HDLC ✔ Balanced approach to algorithm Bus Interrupts and efficiency Bridge GPIO CrunchTM Engine Clocks ✔ Floating point, integer and signal and ARM920T Ti
Slide 7: MaverickCrunch Engine (Cont)
TM 9312 MaverickCrunch Engine (Cont) ARM920T Hardware Support Co-Processor ✔ IEEE Single/Double Floating Point Interface ✔ 32/64 Bit Integer Maverick Crunch ✔ Add/Multiply/Compare 16 x 64b Register File ✔ Integer MAC 32-bit input with with Interlocks 72 bit accumulate Source Bus ✔ Integer Shifts ✔ F
Slide 8: MaverickCrunch Engine (Cont)
TM 9312 MaverickCrunch Engine (Cont) Single Code Stack for Control ;Floating point example ;R2 points to start of filter data block and Computation ;R3 points to start of filter coefficient block ;R4 points to scale factors ;R5 points to stored value ✔ ARM handles loop and addressing ;Loop setup ✔ M
Slide 9: MaverickLock Security
9312 MaverickLockTM Security Serial Ports Secrets stay Secret ✔ Unique emulation technology allows 3 Port USB Ethernet UARTs (3) w/ I2 S MAC SPI Host CPU to create locked Cache/MMU HDLC entries without internal or external Interrupts Bus and Bridge memory GPIO CrunchTM Engine Clocks ✔ 256 bits of la
Slide 10: MaverickLock Security (Cont)
9312 MaverickLockTM Security (Cont) Single IC provides secure ARM 920T Instruction Date hardware environment Cache Cache Locked Locked ✔ General architecture that can be used by partner security Instruction Data ARM 9tdmi Table Table CPU vendors Locked Locked ✔ Combination of boot ROM, laser fuses a
Slide 11: Single Crystal / Multiple Clocks
9312 Single Crystal / Multiple Clocks 3.6864 MHz Wide choice of input sources External Clock OSC 4.0000 MHz 12.288 MHz ✔ 3.6864 MHz ✔ 4.0 MHz ✔ 12.288 MHz ✔ Many other viable options Clock Clock Clock Divider Divider Divider Multiple clock requirements ✔ Independent processor & video clocks PLL PLL
Slide 12: Interfaces
9312 Memory & Storage Interfaces Serial Ports SDRAM interface (unified memory) 3 Port UARTs Ethernet I2 S USB (3) w/ ✔ 1-4 banks of 66 or 100 MHz SDRAM Host MAC HDLC SPI ✔ 16 or 32-bit data path Bus Interrupts and Bridge ✔ Separate display refresh port GPIO CrunchTM Engine Clocks and EIDE interface
Slide 13: Serial Communications Ports
9312 Serial Communications Ports Serial Ports Ethernet Media Access Controller 3 Port UARTs ✔ Media independent interface to external PHY USB Ethernet MAC (3) w/ I2 S SPI ✔ 1, 10, 100 Mbps operation Host HDLC ✔ HPNA 1.0 compatible Bus Interrupts and Bridge GPIO 3 port USB host CrunchTM Engine Clocks
Slide 14: User Interfaces
9312 User Interfaces Serial Ports LCD interface ✔ 4, 8, 16, 18 bits per pixel 3 Port USB Ethernet UARTs (3) w/ I2 S MAC SPI ✔ Dedicated SDRAM memory port Host HDLC ✔ Pulse width modulated brightness control Bus Interrupts and Bridge ✔ 6-bit DAC for LCD contrast control GPIO CrunchTM Engine Clocks an
Slide 15: Vital Statistics
9312 Vital Statistics ● Transistor count ~ 5.7 million ● Process - 0.25u, single poly, 4 metal (6SF) ● Supply voltages - 2.5V core, 3.3V pads ● Processor speed - 200 MHz ● Bus speed - 100 MHz ● Package - 20x20 PBGA, 352 pin ● Pads - 332 on 65u pitch ● Power dissipation - <1.5W 15
Slide 16: Digital Audio Jukebox
9312 Digital Audio Jukebox Serial Ports I2S Codec SPI DAA 3 Port UARTs I2 S Ethernet USB (3) w/ SPI MAC Host HDLC IR Keyboard or Interrupts HPNA Remote Control Bus and Bridge GPIO CrunchTM Engine Clocks and Front ARM920T Timers Panel 16KB I 16KB D Maverick Keypad Cache Cache User Interface Touch MMU