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ARM — Technical Presentation (March 2010)

46 slides from ARM's technical presentation, March 2010

1. Slide 1: On-chip system level visibility: How to optimise ARM platforms & shorten time to market?

   On-chip system level visibility How to optimise ARM platforms & shorten time to market ? Serge Poublan ARM CoreSight product manager Javier Orensanz ARM tools product manager 1

2. Slide 2: Drivers & Usage Cases

   DRIVERS & USAGE CASES The Architecture for the Digital World® ARM

3. Slide 3: Higher level of integration

   Higher level of integration Optimized ARM Smartphone Block Diagram 3

4. Slide 4: Software cost explodes

   Software cost explodes P openstreetap Featured Applications Coresight Trace 6a ay ae fea] (are CODEC Cortex- M3 CPU || Gemma Bluetooth ARMI68 Ca wifi 802.11 Design Cost ($M) 2 r} 60 re a o = (sto) a Y a om sing Audio || Controier || _ Flash Applications Controter||_*!_] Corsex-MO exc (Usa ore PU Pro

5. Slide 5: Many users need on-chip visibility

   Many users need on-chip visibility 5

6. Slide 6: Visibility for all with CoreSight

   Visibility for all with CoreSight™ 6

7. Slide 7: Wide industry support

   Wide industry support ReaWview |S KEN coccron alae /amengen asnine Toasty AR Tools by ARM sey (Sartre BITRAN ett commuter rim, tt, meee SIAR ~ 1 SYSTEM a RASONANCE RONETOX == Cortex: M3.CPU | dam Bluetooth ARM968 CPU | emp won 802.11 == i Mali400 || Mali-vE || LCD Video GPU || Video || Interface cop

8. Slide 8: CoreSight: an overview

   CoreSight™: an overview AMBA AXI Example ARM SoC APB bridge Cortex Cortex DSP A9 R4 Shared Port peripherals 8

9. Slide 9: CoreSight & real-time trace

   CoreSight & real-time trace System Trace AMBA AXI Example ARM SoC APB bridge Cortex Cortex DSP A9 R4 System Bus trace trace Shared Port CPU Trace CPU Trace DSP ETM peripherals Processor Trace Source Code associated coverage instructions Cycles per instruction Interlock information 9

10. Slide 10: CoreSight & multi-core debug

    CoreSight & multi-core debug Cost effective debug AMBA AXI Example Cross trigger matrix ARM SoC APB bridge Cortex Cortex Cross Trigger Cross Trigger Cross Trigger DSP A9 R4 Interface Interface Interface SWD DAP Shared Port peripherals Debug bus (APB) Debug control bus RealView ICE RealView Trace 10

11. Slide 11: CoreSight & trace management

    CoreSight & trace management System Trace Cost effective debug AMBA AXI Example Cross trigger matrix ARM SoC APB bridge Cortex Cortex Cross Trigger Cross Trigger Cross Trigger DSP A9 R4 System Interface Interface Interface SWD DAP Bus trace trace Shared Port CPU Trace CPU Trace DSP ETM peripherals D

12. Slide 12: Debug Interface

    DEBUG INTERFACE The Architecture for the Digital World® ARM

13. Slide 13: Debug: it is all about cost!

    Debug …. It is all about cost!  A mature, simple and low cost 2 pin debug interface  2 pins (clock & data), a simple protocol  Optimised to access memory mapped debug devices  Fully synchronous for high performance (100Mhz) & synthesis  Over 20 tools vendors support SWD  Multi-drop support wit

14. Slide 14: System Trace

    SYSTEM TRACE The Architecture for the Digital World® ARM

15. Slide 15: System level visibility up to the final product

    System level visibility up to the final product  CoreSight System Trace Macrocell  For system & application level debug & optimisation  Deployable up to end product at very low cost Funnel 15

16. Slide 16: System level visibility up to the final product

    System level visibility up to the final product  CoreSight System Trace Macrocell  For system & application level debug & optimisation  Deployable up to end product at very low cost  A single resource for  High level application software view (Apps, kernel, firmware) Funnel 16

17. Slide 17: System level visibility up to the final product

    System level visibility up to the final product  CoreSight System Trace Macrocell  For system & application level debug & optimisation  Deployable up to end product at very low cost  A single resource for  High level application software view (Apps, kernel, firmware)  Tuning of system performa

18. Slide 18: System level visibility up to the final product

    System level visibility up to the final product  CoreSight System Trace Macrocell  For system & application level debug & optimisation  Deployable up to end product at very low cost  A single resource for  High level application software view (Apps, kernel, firmware)  Tuning of system performa

19. Slide 19: High level view for software developers

    High level view for software developers  High performance “hardware printf” with minimum intrusion  Focus on “key part” of your s/w code  Monitor the whole system not only CPU  Comply with MIPI® STPv2  Linux drivers & libraries  Decrease tooling cost 19

20. Slide 20: Trace Management

    TRACE MANAGEMENT The Architecture for the Digital World® ARM

21. Slide 21: Cost effective trace collection

    Cost effective trace collection  CoreSight merges trace sources to CPU Trace CPU Trace reduce packaging cost Bus System Trace Trace Trace bus (ATB) Funnel 21

22. Slide 22: Cost effective trace collection

    Cost effective trace collection  CoreSight merge trace sources to CPU Trace CPU Trace reduce packaging cost Bus System Trace Trace  Export trace to  Debug pins (2 pins)  Dedicated Trace port (parallel or serial high speed trace) Trace bus (ATB)  Existing functional links Funnel 22

23. Slide 23: Cost effective trace collection

    Cost effective trace collection  CoreSight merge trace sources to CPU Trace CPU Trace reduce packaging cost Bus System Trace Trace  Export trace to  Debug pins (2 pins)  Dedicated Trace port (parallel or serial high speed trace) Trace bus (ATB)  Existing functional links Funnel  Capture trace

24. Slide 24: Trace export through 2-pin SWD

    Trace export through 2-pin SWD PTM STM Trace bus (ATB) Funnel Export trace with 2 pins Serial Wire Debug Debug bus (APB) TMC SWD DAP Buffer 24

25. Slide 25: Reduce trace port size with FIFO mode

    Reduce trace port size with FIFO mode PTM STM Trace bus (ATB) Funnel Re-use SRAM for FIFO mode Export trace with 2 pins Serial Wire Debug Debug bus (APB) TMC Buffer FIFO Bits / cycle SWD DAP TPIU Average bandwidth out to allow fitting of a narrower Trace Port Trace Port 25

26. Slide 26: Route trace to existing SoC resources

    Route trace to existing SoC resources PTM STM Trace bus (ATB) Funnel Re-use SRAM for FIFO mode Export trace with 2 pins Serial Wire Debug Debug bus (APB) IO TMC Controller Buffer FIFO Router System SWD DAP Memory AMBA AXI TPIU Average bandwidth out to Route trace to IO controller or allow fitting of

27. Slide 27: Summary

    SUMMARY The Architecture for the Digital World® ARM

28. Slide 28: CoreSight visibility affordable for ALL

    CoreSight™ visibility affordable for ALL  Silicon vendors  Reduce cost of implementing trace  Visibility of signals and software with STM  Output performance and power profiling data  OEMs  High level application software view (Apps, OS, firmware) with STM  Equip more s/w developers with on-c

29. Slide 29: Use of CoreSight enabled hardware for software optimisation

    Use of CoreSight™ enabled hardware for software optimisation Case Study with the ARM Profiler Optimizing Android Media Framework 29

30. Slide 30: Optimization Iterative Process

    Optimization Iterative Process Development Tools Profile Analysis Automatic or manual optimization Source Analyse code Compiler  Compiler  Linker  Assembler  Libraries 01010101 machine code to target 30

31. Slide 31: Trace Capture and Analysis

    Trace Capture and Analysis Processor ETM Trace port USB Compressed Trace port Further SoC trace analyzer compression Host PC  Trace port analyzer compresses and streams trace info  Host PC decompresses and analyzes the trace stream  Profiler displays results of analysis  Profiling and memory usa

32. Slide 32: Case Study – GStreamer FFmpeg execution under Android

    Case Study – GStreamer  FFmpeg execution under Android  Google Android OS: www.android.com  GStreamer multimedia framework: gstreamer.freedesktop.org  FFmpeg audio and video library plug-in: www.ffmpeg.org  Target: Mistral EVM OMAP35xx  Based on Cortex-A8 processor 32

33. Slide 33: Hardware Set Up

    Hardware Set Up The Architecture for the Digital World® ARM

34. Slide 34: ARM Profiler Set Up

    ARM Profiler Set Up Create, manage, and run configurations @ ‘Create a configuration to launch an ARM profiling session, Geax ee {type filter text ] Name: | Android Boot - Profile | 2 Connection» (ei} Images | @ Profiing | IS Environment | [=] Common | Reatview Trace 2 Hi C/C++ Local Application Con

35. Slide 35: ARM Profiler Set Up

    ARM Profiler Set Up “= Connection | [fei Images @ Profiling | IMG Environment | [=] Common | Host Working Directory: | C:\apmDemo | Browse | Target Images io] | C:\apméndroid\kernel. axF ] LoadImage ov Browse | io] | C:\apmAndroid\symbols\system\bin\app_process ] Loaded By OS v Browse | (2) | C:\apm

36. Slide 36: Live Update – Running Android

    Live Update – Running Android Progress of trace collection and analysis Current processes Processor load over time Current threads Processor exceptions over time 36

37. Slide 37: ARM Profiler: Top Level Report

    ARM Profiler: Top Level Report Top 5 threads Top 5 functions 37

38. Slide 38: ARM Profiler: Top Level Report

    ARM Profiler: Top Level Report Instructions Exceptions Mem access Time line 38

39. Slide 39: ARM Profiler: Top Level Report

    ARM Profiler: Top Level Report Details for selected time Time selector Top 5 processes Top 5 threads 39

40. Slide 40: Detailed Views

    Detailed Views  Look at top functions by time, memory access and delay  yuv420p_to_rgb565 is the function to optimize 40

41. Slide 41: Detailed Views

    Detailed Views  Analyze in code view, change and profile again! 41

42. Slide 42: Example: optimise yuv420_to_rgb565

    Example: optimise yuv420_to_rgb565 yuv420_to_rgb565 (image *dst, image *src, int width, int height) for (; height >=2; height -=2) for (; width >=2; width -=2) Process 4 pixels (2x2 square) if odd width  handle last column if odd height  handle last row 42

43. Slide 43: Example: optimise yuv420_to_rgb565

    Example: optimise yuv420_to_rgb565 yuv420_to_rgb565 (image *dst, image *src, int width, int height) for (; height >=2; height -=2) for (; width >=2; width -=2) Process 4 pixels (2x2 square) if odd width  handle last column if odd height  handle last row yuv420_to_rgb565 (image *dst, image *src, in

44. Slide 44: Results

    Results  Hot function: 5% higher performance  Whole application: 3% higher performance 44

45. Slide 45: Conclusion

    Conclusion The Architecture for the Digital World® ARM

46. Slide 46: Conclusion

    Conclusion  CoreSight accelerates SoC developments & reduce time to market  CoreSight is available now on all major open platforms  e.g TI OMAP3, Freescale iMX51, STE Nomadik  And on many ASSP & ASIC  New CoreSight IP makes on-chip visibility affordable for more developers 46

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